register_blocks_cache

Applicability

Product	Supported
Atlas A3 training products/Atlas A3 inference products	√
Atlas A2 training products/Atlas A2 inference products	√
Atlas 200I/500 A2 inference products	x
Atlas inference products	x
Atlas training products	x

Note: For the Atlas A2 training products/Atlas A2 inference products, only the Atlas 800I A2 inference server, Atlas 300I A2 inference card, and A200I A2 Box heterogeneous components are supported.

Function Description

Registers a self-allocated memory in the PagedAttention scenario.

Prototype

register_blocks_cache(cache_desc: CacheDesc, addrs: List[int], blocks_cache_key: Optional[BlocksCacheKey] = None, remote_accessible: Optional[bool] = None) -> Cache:

Parameters

Parameter	Data Type	Description
cache_desc	CacheDesc	Cache description.
addrs	List[int]	Cache address. The total number of addresses in register_cache and register_blocks_cache cannot exceed 240.
blocks_cache_key	Optional[BlocksCacheKey]	Optional index key for BlocksCache (BlocksCacheKey).
remote_accessible	Optional[bool]	Whether the registered memory can be used for network transmission. The default value is True for device memory and False for host memory.

Example

Click Gitcode, select the matching version, and obtain the sample from the examples/python directory.

Returns

In normal cases, the registered cache is returned.

If the input data type is incorrect, a TypeError or ValueError is thrown due to data type mismatch.

If the input parameter is None, an AttributeError is thrown.

Restrictions

For data transmission over HCCS, if the memory is not allocated via aclrtMalloc, the address must be aligned to the page size (2 MB alignment is recommended if the page size is not specified). Otherwise, the link may fail.

Parent topic: CacheManager