register_blocks_cache

Applicable Products

Product	Supported (√/x)
Ascend 950PR/Ascend 950DT	√
Atlas A3 training products/Atlas A3 inference products	√
Atlas A2 training products/Atlas A2 inference products	√
Atlas 200I/500 A2 inference products	x
Atlas inference products	x
Atlas training products	x

Note: For Atlas A2 training products/Atlas A2 inference products, only the Atlas 800I A2 inference server and A200I A2 Box heterogeneous subrack are supported.

Function Description

In the PagedAttention scenario, this API is called to register a self-allocated memory.

Prototype

register_blocks_cache(cache_desc: CacheDesc, addrs: List[int], blocks_cache_key: Optional[BlocksCacheKey] = None, remote_accessible: Optional[bool] = None) -> Cache:

Parameters

Parameter	Data Type	Value Description
cache_desc	CacheDesc	Cache description.
addrs	List[int]	Cache address. The total number of addresses in register_cache and register_blocks_cache cannot exceed 240.
blocks_cache_key	Optional[BlocksCacheKey]	Optional BlocksCacheKey index.
remote_accessible	Optional[bool]	Whether the registered memory can be used for network transmission. The default value is True for device memory and False for host memory.

Example

Click GitCode, select the matching version, and obtain the sample from the examples/python directory.

Returns

In normal cases, the registered cache is returned.

If the input data type is incorrect, the TypeError or ValueError exception is reported due to data type mismatch.

If the input parameter is None, the AttributeError exception is reported.

Constraints

For data transmission over HCCS, if the memory is not allocated via aclrtMalloc, the address must be aligned to the page size (2 MB alignment is recommended if the page size is not specified). Otherwise, the link may fail. This restriction applies to the following products:

Atlas A3 training product/Atlas A3 inference product
Atlas A2 training product/Atlas A2 inference product

None for Ascend 950PR/Ascend 950DTs.

Parent topic: CacheManager