aclrtMemFlush

Product	Supported
Ascend 950PR/Ascend 950DT	√
Atlas A3 training products/Atlas A3 inference products	√
Atlas A2 training products/Atlas A2 inference products	√
Atlas 200I/500 A2 inference products	√
Atlas inference products	√
Atlas training products	√

Flushes cache data to the DDR and invalidates the cache.

In this version, you do not need to care about the cache coherence between the CPU and NPU and therefore this API is unused in this version.

aclError aclrtMemFlush(void *devPtr, size_t size)

Parameter	Input/Output	Description
devPtr	Input	Pointer to the start address of the DDR memory to be flushed to.
size	Input	Size of the DDR memory to be flushed to, in bytes. size cannot be 0.

Parameter

Input/Output

Description

devPtr

Input

Pointer to the start address of the DDR memory to be flushed to.

size

Input

Size of the DDR memory to be flushed to, in bytes.

size cannot be 0.

0 on success; otherwise, failure. For details, see aclError.

Parent topic: Device Memory Allocation and Deallocation