aclrtDevAttr

Definition

      
       
         
         
           typedef enum { 
    ACL_DEV_ATTR_AICPU_CORE_NUM  = 1, 
    ACL_DEV_ATTR_AICORE_CORE_NUM = 101, 
    ACL_DEV_ATTR_CUBE_CORE_NUM = 102,
    ACL_DEV_ATTR_VECTOR_CORE_NUM = 201,      
    ACL_DEV_ATTR_WARP_SIZE = 202,
    ACL_DEV_ATTR_MAX_THREAD_PER_VECTOR_CORE,
    ACL_DEV_ATTR_UBUF_PER_VECTOR_CORE,
    ACL_DEV_ATTR_TOTAL_GLOBAL_MEM_SIZE = 301,
    ACL_DEV_ATTR_L2_CACHE_SIZE,
    ACL_DEV_ATTR_SMP_ID = 401U,
    ACL_DEV_ATTR_PHY_CHIP_ID = 402U,
    ACL_DEV_ATTR_SUPER_POD_DEVICE_ID = 403U,
    ACL_DEV_ATTR_SUPER_POD_SERVER_ID = 404U,
    ACL_DEV_ATTR_SUPER_POD_ID = 405U, 
    ACL_DEV_ATTR_CUST_OP_PRIVILEGE = 406U,
    ACL_DEV_ATTR_MAINBOARD_ID = 407U,
    ACL_DEV_ATTR_IS_VIRTUAL = 501U,
} aclrtDevAttr;

          

        

      
     

**Table 1** Enumeration items
Enumeration Item	Description
ACL_DEV_ATTR_AICPU_CORE_NUM	Number of AI CPUs.
ACL_DEV_ATTR_AICORE_CORE_NUM	Number of AI Cores.
ACL_DEV_ATTR_CUBE_CORE_NUM	Number of Cube Cores.
ACL_DEV_ATTR_VECTOR_CORE_NUM	Number of Vector Cores.
ACL_DEV_ATTR_WARP_SIZE	Number of threads in a warp. In the Single Instruction Multiple Thread (SIMT) programming model, a warp is a set of threads that execute the same instruction. Only Atlas 350 Accelerator Card supports this item. This item is not supported for other product models.
ACL_DEV_ATTR_MAX_THREAD_PER_VECTOR_CORE	Maximum number of threads that can reside on each Vector Core at the same time. Only Atlas 350 Accelerator Card supports this item. This item is not supported for other product models.
ACL_DEV_ATTR_UBUF_PER_VECTOR_CORE	Maximum size of the UB buffer that can be used on each Vector Core, in bytes. Only Atlas 350 Accelerator Card supports this item. This item is not supported for other product models.
ACL_DEV_ATTR_TOTAL_GLOBAL_MEM_SIZE	Total available memory on the device, in bytes.
ACL_DEV_ATTR_L2_CACHE_SIZE	L2 cache size, in bytes.
ACL_DEV_ATTR_SMP_ID	Symmetric multiprocessing (SMP) ID, which is used to identify whether devices run on the same operating system.
ACL_DEV_ATTR_PHY_CHIP_ID	Physical chip ID.
ACL_DEV_ATTR_SUPER_POD_DEVICE_ID	SuperPoD device ID, which identifies a device in a SuperPoD product.
ACL_DEV_ATTR_SUPER_POD_SERVER_ID	SuperPoD server ID, which identifies a server in a SuperPoD product.
ACL_DEV_ATTR_SUPER_POD_ID	SuperPoD ID, which identifies a SuperPoD in the cluster.
ACL_DEV_ATTR_CUST_OP_PRIVILEGE	Whether the custom operator can execute more system call permissions. The options are as follows: 0: The custom operator has limited system call permissions (for example, the write operation cannot be performed). 1: The custom operator can execute more system call permissions. The Atlas 350 Accelerator Card does not support this item.
ACL_DEV_ATTR_MAINBOARD_ID	Mainboard ID.
ACL_DEV_ATTR_IS_VIRTUAL	Whether the Ascend virtual instance is used. 0: A physical machine, instead of the Ascend virtual instance, is used. 1: The Ascend virtual instance is used, which may be a VM or container.

Relationships Between AI Cores, Cube Cores, and Vector Cores

The definition of a Core helps you better understand the relationships between AI Cores, Cube Cores, and Vector Cores. A Core is a compute core with an independent Scalar compute unit. Generally, the Scalar compute unit provides multiple functions for the compute core, such as the single instruction multiple data (SIMD) instruction dispatch. Therefore, the Scalar compute unit is also called the intra-core scheduling unit. The AI data processing core unit varies with products. Currently, there are the following types:

The AI data processing core unit is an AI Core.
- In an AI Core, a Cube and a Vector share a Scalar scheduling unit, for example, Atlas training product .
- In an AI Core, a Cube and a Vector have their own Scalar scheduling units, which are also called a Cube Core and a Vector Core. In this case, a Cube Core and a group of Vector Cores are defined as an AI Core. The number of AI Cores is usually calculated based on the number of Cube Cores, for example, Atlas A2 training product / Atlas A2 inference product .
The AI data processing core unit consists of an AI Core and an independent Vector Core. The AI Core and Vector Core both have independent Scalar scheduling units, for example, Atlas inference product .

Relationships Between SuperPoD IDs, SuperPoD Server IDs, and SuperPoD Device IDs

Parent topic: Data Types and Operation APIs