Interleave

Applicability

Product	Supported
Atlas 350 Accelerator Card	√
Atlas A3 training product / Atlas A3 inference product	x
Atlas A2 training product / Atlas A2 inference product	x
Atlas 200I/500 A2 inference product	x
Atlas inference product AI Core	x
Atlas inference product Vector Core	x
Atlas training product	x

Function Usage

Interleaves the elements in given register tensors srcReg0 and srcReg1 and stores them in dstReg0 and dstReg1. The following figure shows the interleaving mode, where each square represents an element.

Prototype

template <typename T = DefaultType, typename U>
__simd_callee__ inline void Interleave(U& dstReg0, U& dstReg1, U& srcReg0, U& srcReg1)

Parameters

**Table 1** Template parameters
Parameter	Description
T	Data type of the destination and source operands. For the Atlas 350 Accelerator Card, the supported data types are bool, uint8_t, int8_t, uint16_t, int16_t, uint32_t, int32_t, uint64_t, int64_t, half, float, and bfloat16_t.
U	RegTensor type of the source and destination operands, for example, RegTensor<half>. It is automatically inferred by the compiler and does not need to be specified.

**Table 2** Function parameters
Parameter	Input/Output	Description
dstReg0, dstReg1	Output	Destination operand. The type is RegTensor.
srcReg0, srcReg1	Input	Source operand. The type is RegTensor. The source operand must have the same data type as the destination operand.

Constraints

The data types of srcReg0, srcReg1, dstReg0, and dstReg1 must be the same.
srcReg0 and srcReg1 can be the same RegTensor.
dstReg0 and dstReg1 cannot be the same RegTensor.
The source operand and destination operand can be the same RegTensor, for example, Interleave(srcReg0, srcReg1, srcReg0, srcReg1).
For the b64 data type, only RegTraitNumTwo is supported.

Example

template<typename T>
__simd_vf__ inline void InterleaveVF(__ubuf__ T* dst0Addr, __ubuf__ T* dst1Addr, __ubuf__ T* src0Addr, __ubuf__ T* src1Addr, uint32_t oneRepeatSize, uint16_t repeatTimes)
{
    AscendC::Reg::RegTensor<T> srcReg0;
    AscendC::Reg::RegTensor<T> srcReg1;
    AscendC::Reg::RegTensor<T> dstReg0;
    AscendC::Reg::RegTensor<T> dstReg1;
    AscendC::Reg::MaskReg mask = AscendC::Reg::CreateMask<T, AscendC::Reg::MaskPattern::ALL>();               
    for (uint16_t i = 0; i < repeatTimes; i++) {
        AscendC::Reg::LoadAlign(srcReg0, src0Addr + i * oneRepeatSize);
        AscendC::Reg::LoadAlign(srcReg1, src1Addr + i * oneRepeatSize);
        AscendC::Reg::Interleave(dstReg0, dstReg1, srcReg0, srcReg1);
        AscendC::Reg::StoreAlign(dst0Addr + i * oneRepeatSize, dstReg0, mask);
        AscendC::Reg::StoreAlign(dst1Addr + i * oneRepeatSize, dstReg1, mask);
    }
}

Parent topic: Data Rearrangement