ShiftLeft

Applicability

Product	Supported
Atlas 350 Accelerator Card	√
Atlas A3 training product/Atlas A3 inference product	x
Atlas A2 training product/Atlas A2 inference product	x
Atlas 200I/500 A2 inference product	x
Atlas inference product AI Core	x
Atlas inference product Vector Core	x
Atlas training product	x

Function Usage

Perform a left shift operation on the input data srcReg0 based on the mask, according to the corresponding elements of srcReg1, and write the result to dstReg.

Prototype

template <typename T = DefaultType, typename U = DefaultType, MaskMergeMode mode = MaskMergeMode::ZEROING, typename S, typename V>
__simd_callee__ inline void ShiftLeft(S& dstReg, S& srcReg0, V& srcReg1, MaskReg& mask)

Parameters

**Table 1** Template parameters
Parameter	Description
T	Data type of the source operand. For the Atlas 350 Accelerator Card, the supported data types are uint8_t, int8_t, uint16_t, int16_t, uint32_t, int32_t, uint64_t, and int64_t.
U	Data type of the left shift parameter. For the Atlas 350 Accelerator Card, the supported data types are int8_t, int16_t, int32_t, and int64_t. For details about the data type constraints of the source and destination operands, see Table 3.
mode	Set it to MERGING or ZEROING. ZEROING: The elements that are not filtered by mask are set to zero in dst. MERGING: This option is not supported currently.
S	RegTensor type of srcReg0 or dstReg, for example, RegTensor<uint32_t>. It is automatically inferred by the compiler and does not need to be specified.
V	RegTensor type of srcReg1, for example, RegTensor<int32_t>. It is automatically inferred by the compiler and does not need to be specified.

**Table 2** Parameters
Parameter	Input/Output	Description
dstReg	Output	Destination operand. The type is RegTensor.
srcReg0	Input	Source operand. The type is RegTensor. The source operand must have the same data type as the destination operand.
srcReg1	Input	Source operand. The type is RegTensor. The value cannot be a negative number.
mask	Input	Valid indication of the source operand element operation. For details, see MaskReg.

**Table 3** Data type constraints of source and destination operands
Data Type of srcReg0 or dstReg	Data Type of srcReg1
uint8_t	int8_t
uint16_t	int16_t
uint32_t	int32_t
uint64_t	int64_t
int8_t	int8_t
int16_t	int16_t
int32_t	int32_t
int64_t	int64_t

Returns

None

Restrictions

For a logical shift (unsigned data type), if the shift amount is greater than the bit width of the data type, the output is 0.
For an arithmetic shift (signed data type), if both srcReg0 and srcReg1 are less than 0 and the shift amount is greater than the bit width of the data type, the output is –1. If srcReg0 is greater than 0 and the shift amount is greater than the bit width of the data type, the output is 0.

Examples

template<typename T, typename U>
__simd_vf__ inline void ShiftLeftVF(__ubuf__ T* dstAddr, __ubuf__ T* src0Addr, __ubuf__ U* src1Addr, uint32_t count, uint32_t oneRepeatSize, uint16_t repeatTimes)
{
    AscendC::Reg::RegTensor<T> srcReg0;
    AscendC::Reg::RegTensor<U> srcReg1;
    AscendC::Reg::RegTensor<T> dstReg;
    AscendC::Reg::MaskReg mask;
    for (uint16_t i = 0; i < repeatTimes; i++) {
        mask = AscendC::Reg::UpdateMask<T>(count);
        AscendC::Reg::LoadAlign(srcReg0, src0Addr + i * oneRepeatSize);
        AscendC::Reg::LoadAlign(srcReg1, src1Addr + i * oneRepeatSize);       
        AscendC::Reg::ShiftLeft(dstReg, srcReg0, srcReg1, mask);
        AscendC::Reg::StoreAlign(dstAddr + i * oneRepeatSize, dstReg, mask);
    }
}

Parent topic: Logical Computation