MaskReg
Function Usage
Indicates which elements are involved in the computation. The width is one-eighth (VL/8) of the RegTensor.
Prototype
1 2 3 4 5 | template <typename T, MaskPattern mode = MaskPattern::ALL, const RegTrait& regTrait = RegTraitNumOne> __simd_callee__ inline MaskReg CreateMask(); template <typename T, const RegTrait& regTrait = RegTraitNumOne> __simd_callee__ inline MaskReg UpdateMask(uint32_t& scalarValue); |
Parameters
Parameter |
Input/Output |
Description |
|---|---|---|
T |
Input |
Template parameter. The supported data types are b8, b16, b32, and b64. |
mode |
Input |
Mode for creating MaskReg. The value is of the enum class type. enum class MaskPattern {
ALL, // All elements are set to True.
VL1, // At least one element is contained.
VL2, // At least two elements are contained.
VL3, // At least three elements are contained.
VL4, // At least four elements are contained.
VL8, // At least eight elements are contained.
VL16, // At least 16 elements are contained.
VL32, // At least 32 elements are contained.
VL64, // At least 64 elements are contained.
VL128, // At least 128 elements are contained.
M3, // a multiple of 3
M4, // a multiple of 4
H, // At least half of the elements are contained.
Q, // At least a quarter of the elements are contained.
ALLF = 15 // All elements are set to false.
};
|
regTrait |
Input |
This parameter can be set to RegTraitNumOne or RegTraitNumTwo, and the value can only be of the b64 or complex32 data type. The parameter meaning must be consistent with regTrait in the RegTensor template. This parameter is used together with regTrait of RegTensor. If regTrait is set to RegTraitNumOne, the current MaskReg can cover 256 bytes (the length of a VL). For the b64 RegTensor instruction that uses RegTraitNumOne, the generated b64 mask is valid every eight bits. RegTraitNumTwo indicates that the current MaskReg can cover 512 bytes (the length of two VLs). The generated b64 mask is valid every four bits and applies to the b64 RegTensor instruction that uses RegTraitNumTwo. The default value is RegTraitNumOne. |
scalarValue |
Input/Output |
Number of elements required in vector computation, which is used to generate the corresponding MaskReg. The valid range of elements is from 0 to VL_T (the number of T-type elements with a bit width of VL). After this function is executed, VL_T is subtracted from scalarValue. scalarValue = (scalarValue < VL_T) ? 0 : (scalarValue - VL_T) |
Returns
MaskReg
Availability
Atlas 350 Accelerator Card
Restrictions
None
Examples
AscendC::Reg::RegTensor<uint32_t> srcReg;
AscendC::Reg::MaskReg mask0 = AscendC::Reg::CreateMask<uint32_t,AscendC::Reg:: MaskPattern::ALL >();
AscendC::Reg::MaskReg mask1;
uint32_t scalarValue = 127;
for (uint16_t i = 0; i < 2; i++) {
mask1 = AscendC::Reg::UpdateMask<uint32_t>(scalarValue);
AscendC::Reg::LoadAlign<T, AscendC::Reg::PostLiteral::POST_MODE_UPDATE>(srcReg, srcAddr, 0);
AscendC::Reg::Adds(srcReg, srcReg, 1, mask0);
AscendC::Reg::StoreAlign<T, AscendC::Reg::PostLiteral::POST_MODE_UPDATE>(dst0Addr, srcReg, 0, mask0);
AscendC::Reg::StoreAlign<T, AscendC::Reg::PostLiteral::POST_MODE_UPDATE>(dst1Addr, srcReg, 0, mask1);
}