NOT

Applicability

Function Usage

Corresponds to two APIs, used for operations on RegTensor and MaskReg, respectively:

• Operations on RegTensor:

  Perform a bitwise NOT operation on each valid data element in the input srcReg, and write the result to dstReg.

• Operations on MaskReg:

  Perform a bitwise NOT operation on each valid bit in the input src, and write the result to dst.

Prototype

• Operations on RegTensor

  template <typename T = DefaultType, MaskMergeMode mode = MaskMergeMode::ZEROING, typename U>
  __simd_callee__ inline void Not(U& dstReg, U& srcReg, MaskReg& mask)

Parameters

• Operations on RegTensor

  Table 1 Template parameters

  Parameter	Description
  T	Operand data type. For the Atlas 350 Accelerator Card, the supported data types are int8_t, uint8_t, int16_t, uint16_t, int32_t, uint32_t, int64_t, uint64_t, half, and float.
  mode	Set it to MERGING or ZEROING. ZEROING: The elements that are not filtered by mask are set to zero in dst. MERGING: This option is not supported currently.
  U	RegTensor type of the destination operand, for example, RegTensor<half>. It is automatically inferred by the compiler and does not need to be specified.

  Table 2 Parameters

  Parameter	Input/Output	Description
  dstReg	Output	Destination operand. The type is RegTensor.
  srcReg	Input	Source operand. The type is RegTensor. The source operand must have the same data type as the destination operand.
  mask	Input	Valid indication of the source operand element operation. For details, see MaskReg.

Returns

None

Restrictions

None

Examples

• Operations on RegTensor

  template <typename T>
  __simd_vf__ inline void NotVF(__ubuf__ T* dstAddr, __ubuf__ T* srcAddr, uint32_t count, 
   uint32_t oneRepeatSize, uint16_t repeatTimes)
  {
      AscendC::Reg::RegTensor<T> srcReg;
      AscendC::Reg::RegTensor<T> dstReg;
      AscendC::Reg::MaskReg mask;
      for (uint16_t i = 0; i < repeatTimes; i++) {
          mask = AscendC::Reg::UpdateMask<T>(count);
          AscendC::Reg::LoadAlign(srcReg, srcAddr + i * oneRepeatSize);
          AscendC::Reg::Not(dstReg, srcReg, mask);
          AscendC::Reg::StoreAlign(dstAddr + i * oneRepeatSize, dstReg, mask);
      }
  }

• Operations on MaskReg

  template <typename T>
  __simd_vf__ inline void NotVF(__ubuf__ T* dstAddr, __ubuf__ T* srcAddr, uint32_t count, uint32_t oneRepeatSize, uint16_t repeatTimes)
  {
      AscendC::Reg::RegTensor<T> srcReg;
      AscendC::Reg::MaskReg src = AscendC::Reg::CreateMask<T, AscendC::Reg::MaskPattern::ALLF>();
      AscendC::Reg::MaskReg dst;
      AscendC::Reg::MaskReg mask;
      for (uint16_t i = 0; i < repeatTimes; ++i) {
          mask = AscendC::Reg::UpdateMask<T>(count);
          AscendC::Reg::LoadAlign(srcReg, srcAddr + i * oneRepeatSize);
          AscendC::Reg::Not(dst, src, mask);
          AscendC::Reg::Adds(srcReg, srcReg, 0, dst);
          AscendC::Reg::StoreAlign(dstAddr + i * oneRepeatSize, srcReg, mask);
      }
  }