CrossCoreWaitFlag (ISASI)

Product	Supported/Unsupported
Atlas A3 training products/Atlas A3 inference products	√
Atlas A2 training products/Atlas A2 inference products	√
Atlas 200I/500 A2 inference products	x
Atlas inference product's AI Core	x
Atlas inference product's Vector Core	x
Atlas training products	x

Inter-core synchronization control API for the split mode. This API works with CrossCoreSetFlag. For details, see CrossCoreSetFlag.

template <uint8_t modeId = 0, pipe_t pipe = PIPE_S>
__aicore__ inline void CrossCoreWaitFlag(uint16_t flagId)

**Table 1** Parameters in the template
Parameter	Description
modeId	Inter-core synchronization mode. The values are as follows: Mode 0: synchronization control between AI Cores. Mode 1: synchronization control between AIV cores in the AI Core. Mode 2: synchronization control between AIC and AIV cores in the AI Core.
pipe	The pipeline type of the instruction. For details about the pipeline type, see Pipelines.

**Table 2** Parameters
Parameter	Input/Output	Description
flagId	Input	Flag ID of the inter-core synchronization. For the Atlas A2 training products/Atlas A2 inference products, the value ranges from 0 to 10. For the Atlas A3 training products/Atlas A3 inference products, the value ranges from 0 to 10.

None

When using this synchronization API, you need to set the kernel type according to the following rules:
- In the pure Vector/Cube scenario, the kernel type must be set to KERNEL_TYPE_MIX_AIV_1_0 or KERNEL_TYPE_MIX_AIC_1_0.
- In the scenario where the Vector and Cube are used together, the kernel type must be configured based on the actual situation.

CrossCoreWaitFlag must be used together with CrossCoreSetFlag to prevent the computing core from being always in the blocking phase.
If the value of the counter of flagId is 0 when CrossCoreWaitFlag is executed, all instructions after CrossCoreWaitFlag are blocked until the value of the counter of flagId is not 0. The counter of the same flagId can be set for a maximum of 15 times.

For details, see the Examples.

Parent topic: Inter-Core Synchronization