DataSyncBarrier (ISASI)

Supported Products

Product	Supported/Unsupported
Atlas A3 training products/Atlas A3 inference products	x
Atlas A2 training products/Atlas A2 inference products	√
Atlas 200I/500 A2 inference products	√
Atlas inference product's AI Core	x
Atlas inference product's Vector Core	x
Atlas training products	x

Function Usage

Blocks the execution of subsequent instructions until all previous memory access instructions are executed (the memory location to be waited for can be controlled by parameters).

Prototype

template <MemDsbT arg0>
__aicore__ inline void DataSyncBarrier()

Parameters

**Table 1** Parameters in the template
Parameter	Description
arg0	Template parameter, indicating the memory location to be waited for. The type is MemDsbT. The options are as follows: ALL: Wait for all memory access instructions. DDR: Wait for the GM access instruction. UB: Wait for the UB access instruction. SEQ: reserved parameter for future function expansion.

Returns

None

Constraints

None

Example

AscendC::Mmad(...);
AscendC::DataSyncBarrier<MemDsbT::ALL>();
AscendC::Fixpipe(...);

Parent topic: Intra-Core Synchronization