Function: get_devices_topo

Applicability

Product	Supported (√/x)
Atlas A3 training products/Atlas A3 inference products	√
Atlas A2 training products/Atlas A2 inference products	√
Atlas training products	√
Atlas inference products	√
Atlas 200I/500 A2 inference products	√

For the Atlas 200I/500 A2 inference products, this API cannot be called in the Ascend RC form.

Function Usage

Obtains the network topology of the interconnection between two devices.

Prototype

C Prototype

aclError aclrtGetDevicesTopo(uint32_t deviceId, uint32_t otherDeviceId, uint64_t *value)

Python Function

value, ret = acl.rt.get_devices_topo(device_id, other_device_id)

Parameter Description

Parameter	Description
device_id	Int, device ID.
other_device_id	Int, device ID.

Return Value Description

Return Value	Description
ret	Int, 0 on success; else failure.
value	Int, topology of the interconnection between two devices. #define ACL_RT_DEVS_TOPOLOGY_HCCS 0x01ULL # Connected through the Huawei Cache Coherence System (HCCS), which is used for high-speed interconnection between CPUs and NPUs. #define ACL_RT_DEVS_TOPOLOGY_PIX 0x02ULL # Connection through the same PCIe switch #define ACL_RT_DEVS_TOPOLOGY_PIB 0x04ULL # Reserved value #define ACL_RT_DEVS_TOPOLOGY_PHB 0x08ULL # Connection through the PCIe host bridge #define ACL_RT_DEVS_TOPOLOGY_SYS 0x10ULL # Connection through Symmetric Multiprocessing (SMP). NUMA nodes are interconnected through SMP. #define ACL_RT_DEVS_TOPOLOGY_SIO 0x20ULL # Intra-chip connection (Two dies are connected through this mode.) #define ACL_RT_DEVS_TOPOLOGY_HCCS_SW 0x40ULL # Connection through HCCS switch

Return Value

Description

ret

Int, 0 on success; else failure.

value

Int, topology of the interconnection between two devices.

#define ACL_RT_DEVS_TOPOLOGY_HCCS     0x01ULL  # Connected through the Huawei Cache Coherence System (HCCS), which is used for high-speed interconnection between CPUs and NPUs.
#define ACL_RT_DEVS_TOPOLOGY_PIX      0x02ULL  # Connection through the same PCIe switch
#define ACL_RT_DEVS_TOPOLOGY_PIB      0x04ULL  # Reserved value
#define ACL_RT_DEVS_TOPOLOGY_PHB      0x08ULL  # Connection through the PCIe host bridge
#define ACL_RT_DEVS_TOPOLOGY_SYS      0x10ULL  # Connection through Symmetric Multiprocessing (SMP). NUMA nodes are interconnected through SMP.
#define ACL_RT_DEVS_TOPOLOGY_SIO      0x20ULL  # Intra-chip connection (Two dies are connected through this mode.)
#define ACL_RT_DEVS_TOPOLOGY_HCCS_SW  0x40ULL  # Connection through HCCS switch

Parent topic: Device Management