hi_mpi_vpc_flip

Applicability

Product	Supported
Atlas A3 training products/Atlas A3 inference products	√
Atlas A2 training products/Atlas A2 inference products	√
Atlas 200I/500 A2 inference products	√
Atlas inference products	☓
Atlas training products	☓

Description

Flips the input image horizontally, vertically, or in both directions.

Prototype

hi_s32 hi_mpi_vpc_flip (hi_vpc_chn chn, hi_flip_param* flip_param, hi_u32* task_id, hi_s32 milli_sec)

Parameters

Parameter	Input/Output	Description
chn	Input	Channel ID for image processing. Atlas A3 training products/Atlas A3 inference products: The value range of this parameter is [0, 256). The maximum number of channels is 256. Atlas A2 training products/Atlas A2 inference products: The value range of this parameter is [0, 256). The maximum number of channels is 256. Atlas 200I/500 A2 inference products: The value range of this parameter is [0, 128). The maximum number of channels is 128.
flip_param	Input	Flipping information. The input and output image information and the flipping mode are configured in the hi_flip_param structure.
milli_sec	Input	Timeout interval (ms): –1: blocking mode 0: non-blocking mode > 0: timeout interval (timeout mode). The timeout interval varies with the operating system. The deviation is generally within a time slice of an operating system. For example, if the time slice of an operating system is 4 ms and the value of milli_sec is set to 1, the actual timeout interval ranges from 1 ms to 5 ms. When the CPU load is high, the timeout interval may fluctuate.
task_id	Output	Pointer to the task ID, which is used to identify a task.

Returns

0: success
Other values: failure (VPC Return Codes)

Restrictions

The input and output image resolutions must be in the range of [10 × 6, 4096 × 8192], and be the same.

The following input image formats are supported (the output format must be the same as the input format):

HI_PIXEL_FORMAT_YUV_400 = 0,               // YUV400 8bit
HI_PIXEL_FORMAT_YUV_SEMIPLANAR_420 = 1,    // YUV420SP NV12 8bit   
HI_PIXEL_FORMAT_YVU_SEMIPLANAR_420 = 2,    // YUV420SP NV21 8bit 
HI_PIXEL_FORMAT_YUV_SEMIPLANAR_422 = 3,    // YUV422SP 8bit
HI_PIXEL_FORMAT_YVU_SEMIPLANAR_422 = 4,    // YVU422SP 8bit
HI_PIXEL_FORMAT_YUYV_PACKED_422 = 7,       // YUV422Packed YUYV 8bit
HI_PIXEL_FORMAT_UYVY_PACKED_422 = 8,       // YUV422Packed UYVY 8bit
HI_PIXEL_FORMAT_YVYU_PACKED_422 = 9,       // YUV422Packed YVYU 8bit
HI_PIXEL_FORMAT_VYUY_PACKED_422 = 10,      // YUV422Packed VYUY 8bit
HI_PIXEL_FORMAT_YUV_PACKED_444 = 11,       // YUV444 Package  8bit
HI_PIXEL_FORMAT_RGB_888 = 12,              // RGB888
HI_PIXEL_FORMAT_BGR_888 = 13,              // BGR888
HI_PIXEL_FORMAT_ARGB_8888 = 14,            // ARGB_8888
HI_PIXEL_FORMAT_ABGR_8888 = 15,            // ABGR_8888
HI_PIXEL_FORMAT_RGBA_8888 = 16,            // RGBA_8888
HI_PIXEL_FORMAT_BGRA_8888 = 17,            // BGRA_8888
HI_PIXEL_FORMAT_YVU_PLANAR_444 =  22,      // YVU444 Planar 8bit
HI_PIXEL_FORMAT_YVU_PACKED_444 = 58,       // YVU444 Package 8bit
HI_PIXEL_FORMAT_RGB_888_PLANAR = 69,       // RGB888 Planar
HI_PIXEL_FORMAT_BGR_888_PLANAR = 70,       // BGR888 Planar

Parent topic: Vision Preprocessing Core (VPC)