Documentation

Functions

The mobile industry processor interface (MIPI) RX receives raw video data by using low-voltage differential signals, converts the received serial differential signals into digital camera (DC) timings, and then transmit the timings to the downstream video capture (VICAP) module. The MIPI RX supports the MIPI D-PHY, sub-LVDS, and high-speed serial pixel interface (HiSPI) serial video signal inputs.

Defined by SONY corporation, the scalable low voltage signaling embedded clock (SLVS-EC) interface is used to capture image of high frame rate and high resolution. It can convert the high-speed serial data to the DC timing, and then transmit the DC timing to the VICAP module. The SLVS-EC serial video interface provides higher transmission bandwidth, lower power consumption as well as lower data redundancy in batch package. The SLVS-EC interface provides more reliable and stable transmission in application.

The current version supports only the MIPI CSI and SLVS-EC interface.

MIPI RX

MIPI RX is a collection unit that supports multiple differential video input interfaces. It receives data from the MIPI, LVDS, sub-LVDS, and HiSPI interfaces through the combo PHY. MIPI RX supports data transmission at multiple speeds and resolutions by configuring different function modes and supports multiple external input devices.

  • Maximum number of lanes supported by the MIPI RX:

    The MIPI RX supports up to 8-lane MIPI input, 8-lane sub-LVDS input, or eight 8-lane HiSPI input.

  • The MIPI RX can connect to up to four sensors at one time.
  • The MIPI RX can connect to a maximum of different numbers of sensors at the same time, and the lanes required by each sensor are different. Therefore, you need to determine the lane distribution mode of the MIPI RX. For details about the lane distribution mode, see the following table.
    Table 1 MIPI RX lane distribution mode

    Mode

    DEV0

    DEV1

    DEV2

    DEV3

    0

    L0-L7

    N

    N

    N

    1

    L0-L3

    N

    L4-L7

    N

    2

    L0-L3

    N

    L4, L6

    L5, L7

    3

    L0, L2

    L1, L3

    L4, L6

    L5, L7

SLVS-EC

The SLVS-EC interface supports image capture with higher frame rate and resolution. By receiving high-speed serial data through PHY, converting data into the DC timing, and configuring different functional modes, the SLVS-EC can support multiple external input devices and the transmission of data with multiple speeds and resolutions.

SLVS-EC supports up to 8-lane SLVS input.

Lane Pins and Multiplexing

The lane pins of MIPI RX are multiplexed with that of the SLVS-EC. A lane can be used by either the MIPI RX or SLVS-EC at a time.

For details about the lane pin connections, see the following table.
Table 2 Lane multiplexing relationship between MIPI RX and SLVS-EC

LANE

MIPI0

MIPI1

MIPI2

MIPI3

SLVS0

SLVS1

Lane0

√

-

-

-

√

√

Lane1

√

√

-

-

√

√

Lane2

√

-

-

-

√

√

Lane3

√

√

-

-

√

√

Lane4

√

-

√

-

√

√

Lane5

√

-

√

√

√

√

Lane6

√

-

√

-

√

√

Lane7

√

-

√

√

√

√
  • MIPI0 corresponds to VICAP DEV0, MIPI1 corresponds to VICAP DEV1, and so on.
  • SLVS0 corresponds to VICAP DEV0, and SLVS1 corresponds to VICAP DEV1.