HintGraph

HintGraph corresponds to the backend entry phase. To be specific, HintGraph defines the input specifications of the Auto Schedule module. In the HintGraph phase, all memory (including the UB and GM) is considered infinite. Each node is an independent loop used to process the input. In addition, core distribution is not considered in the HintGraph phase, and all operators are computed on the same core. The following HintGraph is used as an example.

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graph LR

Data1 --> Load1 --> Add
Data2 --> Load2 --> Add --> Store --> Output

According to the memory semantics of nodes, the Load output, Add input and output, and Store input should be located in the UB memory, and the Data output should be located in the GM memory. However, the UB memory size is limited. It is impossible to load all the Data output to the UB and then continue to perform the Add operation. However, the HintGraph phase does not focus on the memory size. Therefore, the preceding graph is correct.

In the HintGraph phase, some requirements and conventions are added for AscGraph. If these conventions cannot be met and need to be expressed, the Ascend IR of the FusedAscBackend type can be used to separate the graph into multiple AscGraphs for expression.