Sensor Output

Configure the VI, MIPI, and ISP modules in sequence by referring to Application Development (C&C++). After the entire system runs, you can run the cat /proc/umap/mipi_rx and cat /proc/umap/vi commands to view the debugging information of each module, such as the parameter values delivered by the interface and the variable values during program running.

When multiple slave sensors are used, some of them may require highly precise timing matching between the Vsync and Hsync signals.

When the sync mode is enabled at the VI end, the sensor boot process needs to be specially handled. For example, for the sensor that generates its own Hsync signal while the Vsync signal is generated by the VI end, the Vsync and Hsync timings must strictly match each other.
When the sync mode is enabled at the VI end, the timing of the Vsync signal is changed so that the Vsync signals in multiple channels can be synchronized. In this case, the timing of the Vsync signal is different from that of the Hsync signal, leading to abnormal sensor data output. Therefore, for the sensor that requires highly precise timing matching between the Vsync and Hsync signals, the sensor boot process must be modified. Specifically, before the sync mode is enabled at the VI end, set the sensor to the standby mode first. After the Vsync signals at the VI end are synchronized, set the sensor to the data output mode.

Parent topic: Image Capture