Compile Options

-help

No

Displays the help information.

--npu-arch

Yes

Specifies the AI processor architecture for compile. The value is dav-<arch-version>, where <arch-version> indicates the NPU architecture version number. For details about the architecture version number of each product model, see Table 1.

Currently, only --npu-arch=dav-2201 is supported.

--npu-soc

No

Specifies the AI processor model for compile. If both npu-soc and npu-arch are configured, npu-arch is preferentially enabled.

The AI processor model can be obtained in the following ways:

• For the following products: Run the npu-smi info command on the server where AI processor is installed to obtain the Name information. The actual value is AscendName. For example, if Name is xxxyy, the actual value is Ascendxxxyy.

  Atlas A2 training product/Atlas A2 inference product

  Atlas 200I/500 A2 inference product

  Atlas inference product

  Atlas training product

• For the Atlas A3 training product/Atlas A3 inference product: Run the npu-smi info -t board -i id -c chip_id command on the server where AI processor is installed to obtain the Chip Name and NPU Name information. The actual value is Chip Name_NPU Name. For example, if the value of Chip Name is Ascendxxx and the value of NPU Name is 1234, the actual value is Ascendxxx_1234. Note that:
  • id: device ID, which is the NPU ID obtained by running the npu-smi info -l command.
  • chip_id: chip ID, which is obtained by running the npu-smi info -m command.
• For the Atlas 350 Accelerator Card: Run the npu-smi info -t board -i id command on the server where AI processor is installed to obtain the Chip Name and NPU Name information. The actual value is Chip Name_NPU Name. For example, if the value of Chip Name is Ascendxxx and the value of NPU Name is 1234, the actual value is Ascendxxx_1234.

  id indicates the device ID, which is the NPU ID obtained by running the npu-smi info -l command.

-o <file>

No

Specifies the name and location of the output file.

-c

No

Compiles and generates the target file.

-O

No

Specifies the optimization level of the compiler. Currently, -O3, -O2, and -O0 are supported.

-fPIC

No

Instructs the compiler to generate location-independent code.

-shared, --shared

No

Compiles and generates dynamic link libraries. For details, see Compilation, Link, and Library Usage.

-lib, --cce-build-static-lib

No

Compiles and generates static link libraries. The compiler compiles and links the code on the device to generate a binary file on the device, uses the file as the input for compile on the host, and links the file to generate a static link library. For details, see Compilation, Link, and Library Usage.

--cce-auto-sync

No

Enables automatic synchronization. The execution units in the AI Core are asynchronous and parallel. The read and write operations of the LocalTensor may depend on data. You can use this option to perform automatic synchronization without manually inserting the synchronization by calling the API. For details, see Automatic Synchronization.

--cce-auto-sync-log

No

Outputs the synchronization insertion information to the <file> file by configuring --cce-auto-sync-log to <file>.

--std=c++17

No

Configures the C++ standard. This option is required for the Ascend C operator compile which uses the C++17 standard. If the file name extension is asc, the default value of std is c++17.

-x

No

Parses and compiles the input file following this option based on the specific syntax API. The file name extension can be cce, asc, or aicpu. Ccache compile cache acceleration is not supported. If Ccache is required, use --cce-aicore-lang instead.

--cce-aicore-lang

No

Compiles the input file following this option in CCE heterogeneous language mode. Ccache compile cache acceleration is supported. (This option cannot be used together with -xcce.) For details about the cache acceleration effect, see the Ccache official website.

-g

No

Adds debugging information during compile.

--sanitizer, --cce-enable-sanitizer

No

Adds code correctness verification information during compilation. When the sanitizer option is used, the -g option must be added and cannot be used in the -O0 scenario.

--run-mode=cpu/sim

No

cpu mode: During compile, the device code is also compiled into an executable file that can run on the host. The CPU simulation environment can be used for operator development and testing.

SIM mode: During linking, you can add the implementation library corresponding to the simulation mode so that the code can run in simulation mode. You can view simulation-related logs to facilitate performance debugging.

--cce-long-call=true

No

Enables the long jump function to solve the problem that the call/jump distance is too long and even the thunk generated by the LLD cannot reach the destination. A typical error message is "InputSection too large for range extension thunk."

--cce-soc-version

No

This option will be deprecated in later versions. Do not use this compile option. Use --npu-arch or --npu-soc instead.

Specifies the model of the Ascend AI Processor. If this option is set, the related binary file will be generated.

If the AI processor model cannot be determined, run the npu-smi info command on the server where the AI processor is installed. Add the prefix Ascend to the queried Name. For example, if the value of Name is xxxyy, the actual value is Ascendxxxyy.

--cce-soc-core-type

No

This option will be deprecated in later versions. Do not use this compile option. Use --npu-arch or --npu-soc instead.

Generates a binary file of the core. The value can be VecCore, CubeCore, or AICore.

• VecCore: written Vector code only.
• CubeCore: written Cube code only.
• AICore: written Vector and Cube code.