aclrtGetDevicesTopo

Atlas 350 Accelerator Card

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Atlas A3 training product/Atlas A3 inference product

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Atlas A2 training product/Atlas A2 inference product

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Atlas 200I/500 A2 inference product

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Atlas inference product

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Atlas training product

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deviceId

Input

Device ID.

Must be in the range of [0, Device count – 1]. Call aclrtGetDeviceCount to obtain the device count.

otherDeviceId

Input

Device ID.

Must be in the range of [0, Device count – 1]. Call aclrtGetDeviceCount to obtain the device count.

value

Output

Topology of the interconnection between two devices.

• ACL_RT_DEVS_TOPOLOGY_HCCS: connected through HCCS. Huawei Cache Coherence System (HCCS) is a high-speed interconnection system used between CPUs and NPUs.
• ACL_RT_DEVS_TOPOLOGY_PIX: connected through the same PCIe switch.
• ACL_RT_DEVS_TOPOLOGY_PHB: connected through the PCIe host bridge.
• ACL_RT_DEVS_TOPOLOGY_SYS: connected through Symmetric Multiprocessing (SMP). NUMA nodes are interconnected through SMP.
• ACL_RT_DEVS_TOPOLOGY_SIO: intra-chip connection. Two dies are connected through this mode.
• ACL_RT_DEVS_TOPOLOGY_HCCS_SW: connected through the HCCS switch.
• ACL_RT_DEVS_TOPOLOGY_PIB: reserved value, not supported currently.

The macros are defined as follows:

#define ACL_RT_DEVS_TOPOLOGY_HCCS     0x01ULL
#define ACL_RT_DEVS_TOPOLOGY_PIX      0x02ULL
#define ACL_RT_DEVS_TOPOLOGY_PHB      0x08ULL
#define ACL_RT_DEVS_TOPOLOGY_SYS      0x10ULL
#define ACL_RT_DEVS_TOPOLOGY_SIO      0x20ULL
#define ACL_RT_DEVS_TOPOLOGY_HCCS_SW  0x40ULL
#define ACL_RT_DEVS_TOPOLOGY_PIB      0x04ULL