register_blocks_cache
Applicability
Product |
Supported (√/x) |
|---|---|
Atlas 350 Accelerator Card |
x |
√ |
|
√ |
|
x |
|
x |
|
x |
Note: For
Function Description
In the PagedAttention scenario, this API is called to register a self-allocated memory.
Prototype
1 | register_blocks_cache(cache_desc: CacheDesc, addrs: List[int], blocks_cache_key: Optional[BlocksCacheKey] = None, remote_accessible: Optional[bool] = None) -> Cache: |
Parameters
Parameter |
Data Type |
Description |
|---|---|---|
cache_desc |
Cache description. |
|
addrs |
List[int] |
Cache address. The total number of addresses in register_cache and register_blocks_cache cannot exceed 240. |
blocks_cache_key |
Optional[BlocksCacheKey] |
Optional BlocksCacheKey index. |
remote_accessible |
Optional[bool] |
Whether the registered memory can be used for network transmission. The default value is True for device memory and False for host memory. |
Example
Click GitCode, select the matching version, and obtain the sample from the examples/python directory.
Returns
In normal cases, the registered cache is returned.
If the input data type is incorrect, the TypeError or ValueError exception is thrown due to data type mismatch.
If the input parameter is None, the AttributeError exception is reported.
Restrictions
For data transmission over HCCS, if the memory is not allocated via aclrtMalloc, the address must be aligned to the page size (2 MB alignment is recommended if the page size is not specified). Otherwise, the link may fail. This restriction applies to the following products:
Atlas A3 training product /Atlas A3 inference product Atlas A2 training product /Atlas A2 inference product