ReduceDataBlock

Applicability

Product	Supported
Atlas 350 Accelerator Card	√
Atlas A3 training product/Atlas A3 inference product	x
Atlas A2 training product/Atlas A2 inference product	x
Atlas 200I/500 A2 inference product	x
Atlas inference product AI Core	x
Atlas inference product Vector Core	x
Atlas training product	x

Function Usage

Sums the elements involved in the computation in each data block (32 bytes) when ReduceType is SUM, and stores the final results in the least significant bits of dstReg in sequence.

Computes the maximum value in each data block (32 bytes) when ReduceType is MAX, and stores the final results in the least significant bits of dstReg in sequence.

Computes the minimum value in each data block (32 bytes) when ReduceType is MIN, and stores the final results in the least significant bits of dstReg in sequence.

Prototype

template <ReduceType type = ReduceType::SUM, typename T = DefaultType, MaskMergeMode mode = MaskMergeMode::ZEROING, typename U>
__simd_callee__ inline void ReduceDataBlock(U& dstReg, U srcReg, MaskReg mask)

Parameters

**Table 1** Template parameters
Parameter	Description
type	ReduceType type. SUM, MAX, and MIN are supported. enum class ReduceType { SUM = 0, MAX, MIN, };
T	Data type of the destination and source operands. For the Atlas 350 Accelerator Card, the supported data types are int16_t, uint16_t, half, int32_t, uint32_t, and float.
mode	Set it to MERGING or ZEROING. Currently, only ZEROING is supported. ZEROING: The elements that are not filtered by mask are set to zero in dst.
U	RegTensor type of the source and destination operands, for example, RegTensor<int32_t>. It is automatically inferred by the compiler and does not need to be specified.

**Table 2** Function parameters
Parameter	Input/Output	Description
dstReg	Output	Destination operand. The type is RegTensor.
srcReg	Input	Source operand. The type is RegTensor.
mask	Input	Valid indication of the source operand element operation. For details, see MaskReg.

Constraints

None

Example

template<typename T>
__simd_vf__ inline void ReduceDataBlockVF(__ubuf__ T* dstAddr, __ubuf__ T* srcAddr, uint32_t count, 
 uint32_t oneRepeatSize, uint16_t repeatTimes)
{
    AscendC::Reg::RegTensor<T> srcReg;
    AscendC::Reg::RegTensor<T> dstReg;
    AscendC::Reg::MaskReg mask;
    for (uint16_t i = 0; i < repeatTimes; i++) {
        AscendC::Reg::LoadAlign(srcReg, srcAddr + i * oneRepeatSize);
        mask = AscendC::Reg::UpdateMask<T>(count);
        // type = ReduceType::SUM
        AscendC::Reg::ReduceDataBlock<AscendC::Reg::ReduceType::SUM>(dstReg, srcReg, mask);
        // type = ReduceType::MAX
        // AscendC::Reg::ReduceDataBlock<AscendC::Reg::ReduceType::MAX>(dstReg, srcReg, mask);
        // type = ReduceType::MIN
        // AscendC::Reg::ReduceDataBlock<AscendC::Reg::ReduceType::MIN>(dstReg, srcReg, mask);
        AscendC::Reg::StoreAlign(dstAddr + i * oneRepeatSize, dstReg, mask); 
    }
}

Parent topic: Reduction Computation