Mul

Applicability

Product

Supported

Atlas 350 Accelerator Card

Atlas A3 training product/Atlas A3 inference product

x

Atlas A2 training product/Atlas A2 inference product

x

Atlas 200I/500 A2 inference product

x

Atlas inference product AI Core

x

Atlas inference product Vector Core

x

Atlas training product

x

Function Usage

Multiplies the input data srcReg0 and srcReg1 element-wise based on the mask and writes the result to dstReg. The formula is as follows:

Prototype

template <typename T = DefaultType, MaskMergeMode mode = MaskMergeMode::ZEROING, typename U>
__simd_callee__ inline void Mul(U& dstReg, U& srcReg0, U& srcReg1, MaskReg& mask)

Parameters

Table 1 Parameters in the template

Parameter

Description

T

Operand data type.

For the Atlas 350 Accelerator Card, the supported data types are uint16_t, int16_t, uint32_t, int32_t, half, float, bfloat16_t, uint64_t, and int64_t, complex32, and complex64.

mode

Set it to MERGING or ZEROING.

  • ZEROING: The elements that are not filtered by mask are set to zero in dstReg.
  • MERGING: This option is not supported currently.

U

RegTensor type of the destination operand, for example, RegTensor<half>. It is automatically inferred by the compiler and does not need to be specified.

Table 2 Parameters

Parameter

Input/Output

Description

dstReg

Output

Destination operand.

The type is RegTensor.

srcReg0

Input

Source operand.

The type is RegTensor.

srcReg1

Input

Source operand.

The type is RegTensor.

mask

Input

Valid indication of the source operand element operation. For details, see MaskReg.

Returns

None

Restrictions

The result is in non-saturation mode.

Examples

template<typename T>
__simd_vf__ inline void MulVF(__ubuf__ T* dstAddr, __ubuf__ T* src0Addr, __ubuf__ T* src1Addr, uint32_t count, uint32_t oneRepeatSize, uint16_t repeatTimes)
{
    AscendC::Reg::RegTensor<T> srcReg0;
    AscendC::Reg::RegTensor<T> srcReg1;
    AscendC::Reg::RegTensor<T> dstReg;
    AscendC::Reg::MaskReg mask;    
    for (uint16_t i = 0; i < repeatTimes; i++) {
        mask = AscendC::Reg::UpdateMask<T>(count);
        AscendC::Reg::LoadAlign(srcReg0, src0Addr + i * oneRepeatSize);
        AscendC::Reg::LoadAlign(srcReg1, src1Addr + i * oneRepeatSize);
        AscendC::Reg::Mul(dstReg, srcReg0, srcReg1, mask);
        AscendC::Reg::StoreAlign(dstAddr + i * oneRepeatSize, dstReg, mask);
    }
}