register_cache

Applicable Products

Product

Supported (√/x)

Ascend 950PR/Ascend 950DT

√

Atlas A3 training products/Atlas A3 inference products

√

Atlas A2 training products/Atlas A2 inference products

√

Atlas 200I/500 A2 inference products

x

Atlas inference products

x

Atlas training products

x

Note: For Atlas A2 training products/Atlas A2 inference products, only the Atlas 800I A2 inference server and A200I A2 Box heterogeneous subrack are supported.

Function Description

In the non-PagedAttention scenario, this API is called to register a self-allocated memory.

Prototype

1
register_cache(cache_desc: CacheDesc, addrs: List[int], cache_keys: Union[Tuple[CacheKey], List[CacheKey]] = (), remote_accessible: Optional[bool] = None) -> Cache:

Parameters

Parameter

Data Type

Value Description

cache_desc

CacheDesc

Cache description.

addrs

List[int]

Cache address. The total number of addresses in register_cache and register_blocks_cache cannot exceed 240.

cache_keys

Union[Tuple[CacheKey], List[CacheKey]]

Cache index.

remote_accessible

Optional[bool]

Whether the registered memory can be used for network transmission. The default value is True for device memory and False for host memory.

Example

Click GitCode, select the matching version, and obtain the sample from the examples/python directory.

Returns

In normal cases, the registered cache is returned.

If the input data type is incorrect (src and dst do not match), the TypeError or ValueError exception is reported.

If the input parameter is None, the AttributeError exception is reported.

Constraints

The device memory must be registered before link establishment, while the host memory has no restrictions on the order of operations.

The registered memory address must be unique.

A maximum of 50 GB device memory and 20 GB host memory can be registered. Larger registered memory results in higher OS memory usage. This restriction applies to the following products:

  • Atlas A2 training products/Atlas A2 inference products
  • Atlas A3 training products/Atlas A3 inference products

For D2D data transmission over HCCS, the start address must be aligned to 2 MB; otherwise, the link API may fail. HCCS does not support host memory. This restriction applies to the following products:

  • Atlas A2 training products/Atlas A2 inference products
  • Atlas A3 training products/Atlas A3 inference products

For RDMA data transmission, host memory must be allocated using the aclrtMallocHost API; otherwise, the link API may fail. This restriction applies to the following products:

  • Atlas A2 training products/Atlas A2 inference products
  • Atlas A3 training products/Atlas A3 inference products