aclrtMemMallocPolicy

A single enumeration item or multiple enumeration items are supported.

Configure a single enumeration item:
If a value other than ACL_MEM_TYPE_LOW_BAND_WIDTH and ACL_MEM_TYPE_HIGH_BAND_WIDTH is configured, the system allocates memory from either the high-bandwidth or low-bandwidth physical memory, depending on the hardware situation.
- ACL_MEM_MALLOC_HUGE_FIRST
- ACL_MEM_MALLOC_HUGE_ONLY
- ACL_MEM_MALLOC_NORMAL_ONLY
- ACL_MEM_MALLOC_HUGE_FIRST_P2P
- ACL_MEM_MALLOC_HUGE_ONLY_P2P
- ACL_MEM_MALLOC_NORMAL_ONLY_P2P
- ACL_MEM_MALLOC_HUGE1G_ONLY
- ACL_MEM_MALLOC_HUGE1G_ONLY_P2P
- ACL_MEM_TYPE_LOW_BAND_WIDTH = 0x0100U
- ACL_MEM_TYPE_HIGH_BAND_WIDTH = 0x1000U
- ACL_MEM_ACCESS_USER_SPACE_READONLY = 0x100000U
If ACL_MEM_TYPE_LOW_BAND_WIDTH or ACL_MEM_TYPE_HIGH_BAND_WIDTH is configured, the system uses ACL_MEM_MALLOC_HUGE_FIRST by default and preferentially allocates huge pages.
Configure multiple enumeration item bits or:
You can select one of the following two groups (for example, ACL_MEM_MALLOC_HUGE_FIRST | ACL_MEM_TYPE_HIGH_BAND_WIDTH):
- ACL_MEM_MALLOC_HUGE_FIRST, ACL_MEM_MALLOC_HUGE_ONLY, ACL_MEM_MALLOC_NORMAL_ONLY
- ACL_MEM_TYPE_LOW_BAND_WIDTH, ACL_MEM_TYPE_HIGH_BAND_WIDTH

Enumeration Item	Description
ACL_MEM_MALLOC_HUGE_FIRST = 0	When the requested memory is less than or equal to 1 MB, only normal page memory will be allocated. When the requested memory is greater than 1 MB, the huge page memory is preferentially allocated, and normal page memory will be allocated only when the huge page memory is insufficient.
ACL_MEM_MALLOC_HUGE_ONLY =1	Allocates only huge page memory. If the huge page memory is insufficient, an error is returned.
ACL_MEM_MALLOC_NORMAL_ONLY = 2	Allocates only normal page memory. If the normal page memory is insufficient, an error is returned.
ACL_MEM_MALLOC_HUGE_FIRST_P2P = 3	Applicable to inter-device memory copy. Prioritize the allocation of huge page memory. If huge page memory is insufficient, allocate normal page memory. Atlas 200I/500 A2 inference products: This item is not supported in the current version.
ACL_MEM_MALLOC_HUGE_ONLY_P2P = 4	Applicable to inter-device memory copy. Allocate only huge page memory. If the huge page memory is insufficient, an error is returned. Atlas 200I/500 A2 inference products: This item is not supported in the current version.
ACL_MEM_MALLOC_NORMAL_ONLY_P2P= 5	Applicable to inter-device memory copy. Allocate only normal page memory. Atlas 200/500 A2 Inference Product: This item is not supported in the current version.
ACL_MEM_TYPE_LOW_BAND_WIDTH = 6	Allocates memory from the high-bandwidth physical memory. Atlas 200I/500 A2 inference products: This item is invalid. By default, the system selects the allocation rule based on hardware-supported memory types.
ACL_MEM_TYPE_HIGH_BAND_WIDTH = 7	Allocates memory from the low-bandwidth physical memory. Atlas 200I/500 A2 inference products: This item is invalid. By default, the system selects the allocation rule based on hardware-supported memory types.
ACL_MEM_MALLOC_HUGE1G_ONLY = 8	Allocates huge page memory with a granularity of 1 GB. If the allocated memory is not a multiple of 1 GB, it is rounded up to the nearest multiple of 1 GB. For example, if 1.9 GB memory is requested, 2 GB memory is actually allocated according to the round-up rule. If this item is configured, only 1 GB huge page memory is allocated. If the 1 GB huge page memory is insufficient, an error is returned. Because 1 GB huge page memory is limited, you can use the ACL_MEM_MALLOC_HUGE_FIRST item to allocate huge page memory. To allocate 1 GB of huge page memory, ACL_MEM_MALLOC_HUGE_ONLY (with a 2 MB allocation granularity) requires 512 (= 1024/2) page tables, while ACL_MEM_MALLOC_HUGE1G_ONLY (with a 1 GB granularity) requires only one page table. The latter effectively reduces the number of page tables and expands the address range of the translation lookaside buffer (TLB), thereby improving the discrete access performance. TLB is a hardware module in the AI processor used for caching. It stores the mapping between the recently used virtual addresses and physical addresses. The Ascend 950PR/Ascend 950DT supports this option. The Atlas A3 training products/Atlas A3 inference products support this option. The Atlas A2 training products/Atlas A2 inference products support this option. The Atlas 200I/500 A2 inference products do not support this option. The Atlas inference products do not support this option. The Atlas training products do not support this option.
ACL_MEM_MALLOC_HUGE1G_ONLY_P2P = 9	Allocates huge page memory in granularity of 1 GB only in the scenario of memory copy between two devices. If the allocated memory is not a multiple of 1 GB, it is rounded up to the nearest multiple of 1 GB. For example, if 1.9 GB memory is requested, 2 GB memory is actually allocated according to the round-up rule. If this item is configured, only 1 GB huge page memory is allocated. If the 1 GB huge page memory is insufficient, an error is returned. Because 1 GB huge page memory is limited, you can use the ACL_MEM_MALLOC_HUGE_FIRST_P2P item to allocate huge page memory. To allocate 1 GB of huge page memory, ACL_MEM_MALLOC_HUGE_ONLY_P2P (with a 2 MB allocation granularity) requires 512 (= 1024/2) page tables, while ACL_MEM_MALLOC_HUGE1G_ONLY_P2P (with a 1 GB granularity) requires only one page table. The latter effectively reduces the number of page tables and expands the address range of the TLB, thereby improving the discrete access performance. TLB is a hardware module in the AI processor used for caching. It stores the mapping between the recently used virtual addresses and physical addresses. The Ascend 950PR/Ascend 950DT supports this option. The Atlas A3 training products/Atlas A3 inference products support this option. The Atlas A2 training products/Atlas A2 inference products support this option. The Atlas 200I/500 A2 inference products do not support this option. The Atlas inference products do not support this option. The Atlas training products do not support this option.
ACL_MEM_ACCESS_USER_SPACE_READONLY = 10	Specifies that the allocated memory is read-only in user mode. Memory modification in user mode would fail.

Parent topic: Data Types and Operation APIs