LogicalAnd
Applicability
Product |
Supported |
|---|---|
Atlas 350 Accelerator Card |
√ |
x |
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x |
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x |
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x |
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x |
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x |
Function Usage
Performs the AND operation by element. If the input data type is not bool, zero is regarded as False, and non-zero data is regarded as True.

Prototype
1 2 | template <const LogicalAndConfig& config = DEFAULT_LOGICAL_AND_CONFIG, typename T, typename U> __aicore__ inline void LogicalAnd(const LocalTensor<T>& dst, const LocalTensor<U>& src0, const LocalTensor<U>& src1, const uint32_t count) |
Parameters
Parameter |
Description |
|---|---|
config |
LogicalAnd algorithm configuration. This is an optional parameter of the LogicalAndConfig type. The code below describes the definition. isReuseSource: This parameter is reserved. Pass the default value false. |
T |
Data type of the destination operand. For the Atlas 350 Accelerator Card, the supported data type is bool. |
U |
Data type of the source operand. For the Atlas 350 Accelerator Card, the supported data types are bool, int8_t, uint8_t, int16_t, uint16_t, half, bfloat16_t, int32_t, uint32_t, float, int64_t, and uint64_t. |
1 2 3 | struct LogicalAndConfig { bool isReuseSource; }; |
Parameter |
Input/Output |
Description |
|---|---|---|
dst |
Output |
Destination operand. The type is LocalTensor, and TPosition can be VECIN, VECCALC, or VECOUT. |
src0, src1 |
Input |
Source operand. The type is LocalTensor, and TPosition can be VECIN, VECCALC, or VECOUT. The source operand must have the same data type as the destination operand. |
count |
Input |
Number of elements involved in the computation. |
Returns
None
Constraints
- The source operand address must not overlap the destination operand address.
- For details about the operand address alignment requirements, see General Address Alignment Restrictions.
Examples
For details about a complete example, see logicaland operator sample.
1 2 3 4 | AscendC::LocalTensor<bool> dst; AscendC::LocalTensor<half> src0, src1; uint32_t count = 512; // Number of elements involved in computation AscendC::LogicalAnd(dst, src0, src1, count); |
1 2 3 4 5 6 7 | Input (src0): [1, 2, 0, -1, -2, 0, 3, 4, 0, -3, -4, 0, 5, 6, 0, -5, -6, 0, ... 0] Input (src1): [1, 0, 2, -1, 0, -2, 3, 0, 4, -3, 0, -4, 5, 0, 6, -5, 0, -6, ... 6] Output (dst): [True, False, False, True, False, False, True, False, False, True, False, False, True, False, False, True, False, False, ... False] |