asc_vf_call

Applicability

Product	Supported
Atlas 350 Accelerator Card	√
Atlas A3 training product/Atlas A3 inference product	x
Atlas A2 training product/Atlas A2 inference product	x
Atlas 200I/500 A2 inference product	x
Atlas inference product AI Core	x
Atlas inference product Vector Core	x
Atlas training product	x

Function Usage

Is used in SIMD programming scenarios to start SIMD vector function (VF) subtasks.

When using asc_vf_call to start SIMD VF subtasks, the subtask function must not be a class member function. Using ordinary functions or static class functions is recommended, and the entry function must be marked with the __simd_vf__ macro.

When using asc_vf_call to start SIMD VF subtasks, only raw pointers and common basic data types can be passed as parameters. Structures and arrays cannot be passed.

Prototype

template <auto funcPtr, typename... Args>
__aicore__ inline void asc_vf_call(Args &&...args)

Parameters

**Table 1** Parameters in the template
Parameter	Description
funcPtr	Specifies the SIMD entry kernel function.
Args	Defines a variable parameter list to pass parameters to the SIMD entry kernel function.

**Table 2** Parameters
Parameter	Input/Output	Description
args	Input	Defines a variable parameter list to pass parameters to the SIMD entry kernel function.

Returns

None

Restrictions

None

Examples

Compute the sum of data in Global Memory.

// SIMD function
__simd_vf__ inline void AddVF(__ubuf__ float* dstAddr, __ubuf__ float* src0Addr, __ubuf__ float* src1Addr, uint32_t count,  uint32_t oneRepeatSize, uint16_t repeatTimes) 
{     
    AscendC::Reg::RegTensor<float> srcReg0;
    AscendC::Reg::RegTensor<float> srcReg0;
    AscendC::Reg::RegTensor<float> dstReg;
    AscendC::Reg::MaskReg mask;
    for (uint16_t i = 0; i < repeatTimes; ++i) {
        mask = AscendC::Reg::UpdateMask<float>(count);
        AscendC::Reg::LoadAlign(srcReg0, src0Addr + i * oneRepeatSize);  
        AscendC::Reg::LoadAlign(srcReg1, src1Addr + i * oneRepeatSize);
        AscendC::Reg::Add(dstReg, srcReg0, srcReg1, mask);
        AscendC::Reg::StoreAlign(dstAddr + i * oneRepeatSize, dstReg , mask);
    }
}

__aicore__ inline void SimdComputeShell()      
{  
     AscendC::LocalTensor<float> dst = outQueueZ.AllocTensor<float>();     
     AscendC::LocalTensor<float> src0 = inQueueX.DeQue<float>();
     AscendC::LocalTensor<float> src1 = inQueueY.DeQue<float>();
     constexpr uint32_t oneRepeatSize = AscendC::GetVecLen()/sizeof(float);
     uint32_t count = 512;
     // Round up and compute repeat.
     uint16_t repeatTimes = AscendC::CeilDivision(count, oneRepeatSize);
     __ubuf__ float* dstAddr = (__ubuf__ float*)dst.GetPhyAddr();
     __ubuf__ float* src0Addr = (__ubuf__ float*)src0.GetPhyAddr();
     __ubuf__ float* src1Addr = (__ubuf__ float*)src1.GetPhyAddr();
     asc_vf_call<AddVF>(dstAddr, src0Addr, src1Addr, count, oneRepeatSize, repeatTimes);
     outQueueZ.EnQue(dst);
     inQueueX.FreeTensor(src0);
     inQueueY.FreeTensor(src1);
}

Parent topic: Reg Vector Computation