aclrtMemAttr
Data Format |
Description |
|---|---|
ACL_DDR_MEM = 0 |
DDR memory, that is, all huge page memory and normal page memory on the DDR |
ACL_HBM_MEM = 1 |
High bandwidth memory, including all huge pages and common pages. |
ACL_DDR_MEM_HUGE = 2 |
DDR hugepage memory. |
ACL_DDR_MEM_NORMAL = 3 |
Normal DDR memory. |
ACL_HBM_MEM_HUGE = 4 |
Huge page of on-chip memory. |
ACL_HBM_MEM_NORMAL = 5 |
Common page of on-chip memory. |
ACL_DDR_MEM_P2P_HUGE = 6 |
Huge page memory for inter-device memory copy. |
ACL_DDR_MEM_P2P_NORMAL = 7 |
Normal page memory for inter-device memory copy. |
ACL_HBM_MEM_P2P_HUGE = 8 |
Huge page memory for inter-device memory copy. |
ACL_HBM_MEM_P2P_NORMAL = 9 |
Normal page memory for inter-device memory copy. |
ACL_HBM_MEM_HUGE1G = 10 |
Huge page, the memory allocation granularity is 1 GB. If the memory is less than 1 GB, it is rounded up to 1 GB. |
ACL_HBM_MEM_P2P_HUGE1G = 11 |
Huge page memory for inter-device memory copy. The memory allocation granularity is 1 GB. If the memory is less than 1 GB, it is rounded up to 1 GB. |
To allocate a huge page of 1 GB, if the allocation granularity is 2 MB, 512 (1024/2) page tables are used. If the allocation granularity is 1 GB, only one page table is used by the huge page of 1 GB. This reduces the number of page tables, expands the address range of the translation lookaside buffer (TLB), and improves the discrete access performance. TLB is a hardware module in the Ascend AI Processor used for caching. It stores the mapping between the recently used virtual addresses and physical addresses.
- The
Atlas training products does not support this option. - The
Atlas inference products does not support this option. - The
Atlas 200I/500 A2 inference products does not support this option. - The
Atlas A2 training products /Atlas A2 inference products supports this option. - The
Atlas A3 training products /Atlas A3 inference products supports this option.