aclrtGetDevicesTopo

Product	Supported
Atlas A3 training products/Atlas A3 inference products	√
Atlas A2 training products/Atlas A2 inference products	√
Atlas 200I/500 A2 inference products	√
Atlas inference products	√
Atlas training products	√

Note: This API cannot be called for Atlas 200I/500 A2 inference products in the Ascend RC form.

Obtains the network topology of the interconnection between two devices.

aclError aclrtGetDevicesTopo(uint32_t deviceId, uint32_t otherDeviceId, uint64_t *value)

Parameter	Input/Output	Description
deviceId	Input	Device ID. Must be in the range of [0, Device count – 1]. Call aclrtGetDeviceCount to obtain the device count.
otherDeviceId	Input	Device ID. Must be in the range of [0, Device count – 1]. Call aclrtGetDeviceCount to obtain the device count.
value	Output	Topology of the interconnection between two devices. Connection through HCCS Huawei Cache Coherence System (HCCS) is a high-speed interconnection system used between CPUs and NPUs. #define ACL_RT_DEVS_TOPOLOGY_HCCS 0x01ULL Connection through the same PCIe switch #define ACL_RT_DEVS_TOPOLOGY_PIX 0x02ULL Connection through the PCIe host bridge #define ACL_RT_DEVS_TOPOLOGY_PHB 0x08ULL Connection through Symmetric Multiprocessing (SMP). NUMA nodes are interconnected through SMP. #define ACL_RT_DEVS_TOPOLOGY_SYS 0x10ULL Intra-chip connection (Two dies are connected through this mode.) #define ACL_RT_DEVS_TOPOLOGY_SIO 0x20ULL Connection through HCCS switch #define ACL_RT_DEVS_TOPOLOGY_HCCS_SW 0x40ULL Reserved value #define ACL_RT_DEVS_TOPOLOGY_PIB 0x04ULL

Parameter

Input/Output

Description

deviceId

Input

Device ID.

Must be in the range of [0, Device count – 1]. Call aclrtGetDeviceCount to obtain the device count.

otherDeviceId

Input

Device ID.

Must be in the range of [0, Device count – 1]. Call aclrtGetDeviceCount to obtain the device count.

value

Output

Topology of the interconnection between two devices.

Connection through HCCS
Huawei Cache Coherence System (HCCS) is a high-speed interconnection system used between CPUs and NPUs.
```
#define ACL_RT_DEVS_TOPOLOGY_HCCS     0x01ULL
```

Connection through the same PCIe switch

#define ACL_RT_DEVS_TOPOLOGY_PIX      0x02ULL

Connection through the PCIe host bridge

#define ACL_RT_DEVS_TOPOLOGY_PHB      0x08ULL

Connection through Symmetric Multiprocessing (SMP). NUMA nodes are interconnected through SMP.
```
#define ACL_RT_DEVS_TOPOLOGY_SYS      0x10ULL
```
Intra-chip connection (Two dies are connected through this mode.)
```
#define ACL_RT_DEVS_TOPOLOGY_SIO      0x20ULL
```

Connection through HCCS switch

#define ACL_RT_DEVS_TOPOLOGY_HCCS_SW  0x40ULL

Reserved value

#define ACL_RT_DEVS_TOPOLOGY_PIB      0x04ULL

0 on success; else, failure. For details, see aclError.

Parent topic: Device Management