General Restrictions

When managing physical memories at different levels, Ascend C uses an abstract logical position (TPosition) to express storage at each level, replacing on-chip physical storage and hiding the hardware architecture. TPosition types include VECIN, VECOUT, VECCALC, A1, A2, B1, B2, CO1 and CO2. For details, see TPosition. Table 1 describes the mapping between TPosition and physical memory.

**Table 1** Mapping between TPosition and physical memory
TPosition	Physical Memory
GM	Global Memory
VECIN	Unified Buffer
VECCALC	Unified Buffer
VECOUT	Unified Buffer
A1	L1 Buffer
A2	L0A Buffer
B1	L1 Buffer
B2	L0B Buffer
C1	Atlas Training Series Product, Unified Buffer.
C2	Atlas Training Series Product, L0C Buffer.
CO1	L0C Buffer
CO2	Atlas Training Series Product, Unified Buffer.
TSCM	L1 Buffer
SPM	Atlas Training Series Product, L1 Buffer.
C2PIPE2GM

The Ascend C memory management module aligns the start address during memory allocation. Table 2 describes the alignment requirements for different types of memory units.

To call the Ascend C APIs for data compute and transfer, the destination and source operands must meet the address offset alignment restrictions specified in Table 2. The start address alignment restrictions specified by an Ascend C instruction API apply in the case of restriction inconsistency.

**Table 2** Alignment requirements for different memory units
Memory Unit	Alignment Requirement
Global Memory	No alignment requirement.
Unified Buffer	32-byte aligned.
L1 Buffer	32-byte aligned.
L0A Buffer/L0B Buffer	512-byte aligned.
L0C Buffer	64-byte aligned.
BT Buffer	64-byte aligned.