Documentation

hi_isp_slave_sns_sync

Description

Defines the configuration of the synchronization signals for the slave mode sensor.

Prototype

typedef struct {
    union {
        struct {
            hi_u32    bit16_reserved : 16; 
            hi_u32    bit_h_inv : 1; 
            hi_u32    bit_v_inv : 1; 
            hi_u32    bit12_reserved : 12; 
            hi_u32    bit_h_enable : 1;
            hi_u32    bit_v_enable : 1;
        } bits;
        hi_u32 bytes;
    } cfg;
    hi_u32    vs_time;
    hi_u32    hs_time;
    hi_u32    vs_cyc; 
    hi_u32    hs_cyc; 
    hi_u32    hs_dly_cyc;
    hi_u32    slave_mode_time;
} hi_isp_slave_sns_sync;

Members

Member

Description

bit16_reserved

Reserved parameter

bit_h_inv

XHS polarity configuration

  • 0: positive;
  • 1: negative.

bit_v_inv

XVS polarity configuration

  • 0: positive
  • 1: negative

bit12_reserved

Reserved parameter

bit_h_enable

XHS output enable

bit_v_enable

XVS output enable

vs_time

XVS signal cycle (unit: cycle of the sensor input clock)

hs_time

XHS signal cycle (unit: cycle of the sensor input clock)

vs_cyc

Valid level width of XVS (unit: cycle of the sensor input clock)

hs_cyc

Valid level width of XHS (unit: cycle of the sensor input clock)

hs_dly_cyc

Delay cycle configuration for the XHS pulse output relative to the XVS pulse (unit: cycle of the sensor input clock)

slave_mode_time

Sensor sequence configuration in slave mode

  • 0: Sensor 0 timing is configured.
  • 1: Sensor 1 timing is configured.
  • 2: Sensor 2 timing is configured.
  • 3: Sensor 3 timing is configured.

Considerations

Figure 2-4 to Figure 2-6 demonstrate the meanings of the configuration parameters of the synchronization signal generation module.

Figure 2-4 Configuration timing diagram of the synchronization signal

Figure 2-5 Polarity inversion of the synchronization signal

Figure 2-6 Synchronization signal enabling