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Moves data from Global Memory (GM) to Level 1 cache (L1).

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• First-n data movement

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• High-dimensional tiling movement

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• Synchronous movement

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None

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PIPE_MTE2

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• The start address of src must be aligned to the number of bytes occupied by the corresponding data type.
• The start address of dst must be 32-byte aligned.
• If multiple asc_copy_gm2l1 instructions need to be executed and the destination addresses of the asc_copy_gm2l1 instructions overlap, a synchronization instruction must be inserted to ensure the serialization of multiple asc_copy_gm2l1 instructions and prevent abnormal data.

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