Inside the AI Core, both the Scalar unit and the DMA unit may access Global Memory.
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As shown in the figure above:
The DMA transfer unit reads and writes Global Memory. Data is exchanged between local memory (such as UB) and Global Memory through interfaces such as asc_copy_ub2gm and asc_copy_gm2ub, with no cache coherence issue. When the Scalar unit accesses Global Memory, it first accesses the Data Cache within each core. Therefore, a cache coherence issue exists between the Data Cache and Global Memory. This interface is used to flush the cache to ensure cache coherence. The usage scenarios are as follows:
When reading data from Global Memory that may have been modified externally by other cores, use the asc_dcci interface to directly access Global Memory and obtain the latest data. When the user writes data to Global Memory through the Scalar unit and wants the data to be written out immediately, the asc_dcci interface must also be used.
When the Scalar unit accesses UB data, this interface must be used together with the interface, with CTRL[49] set to 1'b1 to enable the datacache mode.
[object Object]For the Atlas 350 Accelerator Card, the asc_dcci_entire_ub interface is not supported.
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