UnPack
Applicability
Product |
Supported |
|---|---|
Atlas 350 Accelerator Card |
√ |
x |
|
x |
|
x |
|
x |
|
x |
|
x |
Function Usage
For unsigned integers, writes the elements in the least significant half or most significant half of the source operand srcReg to dstReg with most significant bits filled with 0s to extend the bit width. For signed integers, writes the elements in the least significant half or most significant half of the source operand srcReg to dstReg with the sign bit preserved to extend the bit width.
Prototype
template <typename T = DefaultType, typename U = DefaultType, HighLowPart part = HighLowPart::LOWEST, typename S, typename V> __simd_callee__ inline void UnPack(S& dstReg, V& srcReg)
Parameters
Parameter |
Description |
|---|---|
T |
Data type of the destination operand. For the Atlas 350 Accelerator Card, the supported data types are int16_t, uint16_t, int32_t, uint32_t, int64_t, and uint64_t. For details about the data type constraints of the source operand and destination operand, see Table 3. |
U |
Data type of the source operand. For the Atlas 350 Accelerator Card, the supported data types are int8_t, uint8_t, int16_t, uint16_t, int32_t, and uint32_t. |
part |
Enum type. It is used to specify whether to read the least significant half or most significant half of srcReg.
Note: RegTraitNumTwo supports only the LOWEST mode. |
S |
RegTensor type of the destination operand. |
V |
RegTensor type of the source operand. |
Returns
None
Constraints
None
Example
template<typename T, typename U, int32_t mode>
__simd_vf__ inline void UnPackVF(__ubuf__ T* dstAddr, __ubuf__ U* srcAddr, uint32_t oneDstRepSize, uint16_t repeatTimes, uint32_t oneSrcRepSize)
{
AscendC::Reg::RegTensor<U> srcReg;
AscendC::Reg::RegTensor<T> dstReg;
AscendC::Reg::MaskReg mask = AscendC::Reg::CreateMask<T, AscendC::Reg::MaskPattern::ALL>();
for (uint16_t i = 0; i < repeatTimes; i++) {
AscendC::Reg::LoadAlign(srcReg, srcAddr + i * oneSrcRepSize);
if constexpr (mode == 0) {
AscendC::Reg::UnPack<T, U, AscendC::Reg::HighLowPart::LOWEST>(dstReg, srcReg);
} else if constexpr (mode == 1) {
AscendC::Reg::UnPack<T, U, AscendC::Reg::HighLowPart::HIGHEST>(dstReg, srcReg);
}
AscendC::Reg::StoreAlign(dstAddr + i * oneDstRepSize, dstReg, mask);
}
}