Pack

Applicability

Product	Supported
Atlas 350 Accelerator Card	√
Atlas A3 training product/Atlas A3 inference product	x
Atlas A2 training product/Atlas A2 inference product	x
Atlas 200I/500 A2 inference product	x
Atlas inference product AI Core	x
Atlas inference product Vector Core	x
Atlas training product	x

Function Usage

Selects the 8 least significant bits (for the b16 type), 16 least significant bits (for the b32 type), or 32 least significant bits (for the b64 type) of elements in the source operand srcReg and writes them to the least significant half or most significant half of dstReg.

Prototype

template <typename T = DefaultType, typename U = DefaultType, HighLowPart part = HighLowPart::LOWEST, typename S, typename V>
__simd_callee__ inline void Pack(S& dstReg, V& srcReg)

Parameters

**Table 1** Template parameters
Parameter	Description
T	Data type of the destination operand. For the Atlas 350 Accelerator Card, the supported data types are uint8_t, uint16_t, and uint32_t. For details about the data type constraints of the source operand and destination operand, see Table 3.
U	Data type of the source operand. For the Atlas 350 Accelerator Card, the supported data types are int16_t, uint16_t, int32_t, uint32_t, int64_t, and uint64_t.
part	Enum type. It is used to specify whether to write elements to the least significant half or most significant half of dstReg. HighLowPart::LOWEST: least significant bit mode, which writes elements to the least significant half of dstReg. HighLowPart::HIGHEST: most significant bit mode, which writes elements to the most significant half of dstReg. Note: RegTraitNumTwo supports only the LOWEST mode.
S	RegTensor type of the destination operand. It is automatically inferred by the compiler and does not need to be specified.
V	RegTensor type of the source operand. It is automatically inferred by the compiler and does not need to be specified.

**Table 2** Function parameters
Parameter	Description
dstReg	Destination operand. The type is RegTensor.
srcReg	Source operand. The type is RegTensor.

**Table 3** Mapping between the data types of the source and destination operands
T	U
uint8_t	int16_t
uint8_t	uint16_t
uint16_t	int32_t
uint16_t	uint32_t
uint32_t	int64_t
uint32_t	uint64_t

Returns

None

Constraints

None

Example

template<typename T, typename U, int32_t mode = 0>
__simd_vf__ inline void PackVF(__ubuf__ T* dstAddr, __ubuf__ U* srcAddr, uint32_t oneDstRepSize, uint32_t oneSrcRepSize, uint16_t repeatTimes)
{
    AscendC::Reg::RegTensor<U> srcReg;
    AscendC::Reg::RegTensor<T> dstReg;
    AscendC::Reg::MaskReg mask = AscendC::Reg::CreateMask<T, AscendC::Reg::MaskPattern::ALL>();
    for (uint16_t i = 0; i < repeatTimes; i++) {
        AscendC::Reg::LoadAlign(srcReg, srcAddr + i * oneSrcRepSize);
        if constexpr (mode == 0) {
            AscendC::Reg::Pack<T, U, AscendC::Reg::HighLowPart::LOWEST>(dstReg, srcReg);
        } else if constexpr (mode == 1) {
            AscendC::Reg::Pack<T, U, AscendC::Reg::HighLowPart::HIGHEST>(dstReg, srcReg);
        }
        AscendC::Reg::StoreAlign(dstAddr + i * oneDstRepSize, dstReg, mask);
    }
}

Parent topic: Data Compression