Squeeze

Applicability

Product	Supported
Atlas 350 Accelerator Card	√
Atlas A3 training product/Atlas A3 inference product	x
Atlas A2 training product/Atlas A2 inference product	x
Atlas 200I/500 A2 inference product	x
Atlas inference product AI Core	x
Atlas inference product Vector Core	x
Atlas training product	x

Function Usage

Copies the valid elements selected by mask in the passed srcReg to dstReg in sequence. The valid elements are arranged in ascending order in dstReg. The remaining positions in dstReg are set to 0.

Prototype

template <typename T = DefaultType, GatherMaskMode store = GatherMaskMode::NO_STORE_REG, typename U>
__simd_callee__ inline void Squeeze(U& dstReg, U& srcReg, MaskReg& mask)

Parameters

**Table 1** Template parameters
Parameter	Description
T	Data type of the destination and source operands. For the Atlas 350 Accelerator Card, the supported data types are uint8_t, int8_t, uint16_t, int16_t, uint32_t, int32_t, half, and float.
store	GatherMaskMode specifies whether to store the total number of bytes of valid elements in the AR. For details about the AR, see Table 1. NO_STORE_REG: The total number of bytes of valid elements is not stored in the AR. STORE_REG: The total number of bytes of valid elements is stored in the AR.
U	RegTensor type of srcReg/dstReg, for example, RegTensor<uint32_t>. It is automatically inferred by the compiler and does not need to be specified.

**Table 2** Function parameters
Parameter	Input/Output	Description
dstReg	Output	Destination operand. The type is RegTensor.
srcReg	Input	Source operand. The type is RegTensor.
mask	Input	Controls the elements that participate in computation in each iteration.

Constraints

When the value of store is STORE_REG, the StoreUnAlign and Squeeze instructions must be used alternately due to hardware restrictions. For example:

Squeeze(dstVreg, srcVreg, mask);
StoreUnAlign(dstAddr, dstVreg, ureg);
Squeeze(dstVreg, srcVreg, mask);
StoreUnAlign(dstAddr, dstVreg, ureg);

Example

template<typename T>
__simd_vf__ inline void SqueezeVF(__ubuf__ T* dstAddr, __ubuf__ T* srcAddr, uint32_t oneRepeatSize, uint16_t repeatTimes)
{
    AscendC::Reg::RegTensor<T> srcReg0;
    AscendC::Reg::RegTensor<T> srcReg1;
    AscendC::Reg::UnalignRegForStore ureg;
    AscendC::Reg::MaskReg sqzMask = AscendC::Reg::CreateMask<T, AscendC::Reg::MaskPattern::H>();
    for (uint16_t i = 0; i < repeatTimes; ++i) {
        AscendC::Reg::LoadAlign<T, AscendC::Reg::PostLiteral::POST_MODE_UPDATE>(srcReg0, srcAddr, oneRepeatSize);
        AscendC::Reg::Squeeze<T, AscendC::Reg::GatherMaskMode::STORE_REG>(srcReg1, srcReg0, sqzMask);
        AscendC::Reg::StoreUnAlign<T, AscendC::Reg::PostLiteral::POST_MODE_UPDATE>(dstAddr, srcReg1, ureg);
     }
     AscendC::Reg::StoreUnAlignPost(dstAddr, ureg);
}

Parent topic: Comparison and Selection