PairReduceElem
Applicability
Product |
Supported |
|---|---|
Atlas 350 Accelerator Card |
√ |
x |
|
x |
|
x |
|
x |
|
x |
|
x |
Function Usage
Adds two adjacent values in the passed srcReg and saves the result in the lower bits of dstReg.
Prototype
template <PairReduce type = PairReduce::SUM, typename T = DefaultType, MaskMergeMode mode = MaskMergeMode::ZEROING, typename U> __simd_callee__ inline void PairReduceElem(U& dstReg, U srcReg, MaskReg mask)
Parameters
Parameter |
Description |
|---|---|
type |
Specific PairReduce type. Currently, only sum reduction is supported. enum class PairReduce {
SUM = 0,
};
|
T |
Data type of the destination and source operands. For the Atlas 350 Accelerator Card, the supported data types are half and float. |
mode |
Set it to MERGING or ZEROING.
|
U |
RegTensor type of the destination and source operands. It is automatically inferred by the compiler and does not need to be specified. |
Parameter |
Input/Output |
Description |
|---|---|---|
dstReg |
Output |
Destination operand. The type is RegTensor. |
srcReg |
Input |
Source operand. The type is RegTensor. The source operand must have the same data type as the destination operand. |
mask |
Input |
Valid indication of the source operand element operation. For details, see MaskReg. |
Constraints
None
Example
template<typename T>
__simd_vf__ inline void PairReduceElemVF(__ubuf__ T* dstAddr, __ubuf__ T* srcAddr, uint32_t count,
uint32_t oneRepeatSize, uint16_t repeatTimes)
{
AscendC::Reg::RegTensor<T> srcReg;
AscendC::Reg::RegTensor<T> dstReg;
AscendC::Reg::MaskReg mask;
for (uint16_t i = 0; i < repeatTimes; i++) {
AscendC::Reg::LoadAlign(srcReg, srcAddr + i * oneRepeatSize);
mask = AscendC::Reg::UpdateMask<T>(count);
AscendC::Reg::PairReduceElem<AscendC::Reg::PairReduce::SUM>(dstReg, srcReg, mask);
AscendC::Reg::StoreAlign(dstAddr + i * oneRepeatSize, dstReg, mask);
}
}