MulsCast
Applicability
Product |
Supported |
|---|---|
Atlas 350 Accelerator Card |
√ |
x |
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x |
|
x |
|
x |
|
x |
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x |
Function Usage
Multiplies src by scalar, converts the product to the half type in CAST_ROUND mode, and writes the result to dst based on mask. The formula is as follows:

Prototype
template <typename T0 = DefaultType, typename T1 = DefaultType, typename T2, RegLayout layout = RegLayout::ZERO, typename T3, typename T4> __simd_callee__ inline void MulsCast(T3& dstReg, T4& srcReg, T2 scalarValue, MaskReg& mask)
Parameters
Parameter |
Description |
|---|---|
T0 |
Data type of the destination operand. For the Atlas 350 Accelerator Card, the supported data type is half. |
T1 |
Data type of the source operand. For the Atlas 350 Accelerator Card, the supported data type is float. |
T2 |
Data type of the scalar source operand. For the Atlas 350 Accelerator Card, the supported data type is float. |
layout |
RegLayout enum class. This API supports only RegLayout::ZERO and RegLayout::ONE. This parameter is used when the type of src is half. It does not take effect when the type is float. When the type is half, RegLayout::ZERO indicates that half elements are read from the even bits of b16 RegTensor and converted into float elements, and RegLayout::ONE indicates that half elements are read from the odd bits of b16 RegTensor and converted into float elements. |
T3 |
RegTensor type of dstReg, for example, RegTensor<float>. It is automatically inferred by the compiler and does not need to be specified. |
T4 |
RegTensor type of srcReg, for example, RegTensor<float>. It is automatically inferred by the compiler and does not need to be specified. |
Parameter |
Input/Output |
Description |
|---|---|---|
dstReg |
Output |
Destination operand. The type is RegTensor. |
srcReg |
Input |
Source operand. The type is RegTensor. |
scalarValue |
Input |
Source operand. The type is scalar. |
mask |
Input |
Valid indication of the source operand element operation. For details, see MaskReg. |
Returns
None
Constraints
None
Example
template<typename T>
__simd_vf__ inline void MulsCastVF(__ubuf__ half* dstAddr, __ubuf__ float* srcAddr, float scalarValue, uint32_t count, uint32_t srcRepeatSize, uint32_t dstRepeatSize, uint16_t repeatTimes)
{
AscendC::Reg::RegTensor<float> srcReg0;
AscendC::Reg::RegTensor<half> dstReg0;
AscendC::Reg::MaskReg mask;
for (uint16_t i = 0; i < repeatTimes; i++) {
mask = AscendC::Reg::UpdateMask<float>(count);
AscendC::Reg::LoadAlign(srcReg0, srcAddr + i * srcRepeatSize);
AscendC::Reg::MulsCast<half, float, float, AscendC::Reg::RegLayout::ZERO>(dstReg0, srcReg0, scalarValue, mask);
AscendC::Reg::StoreAlign(dstAddr + i * dstRepeatSize, dstReg0, mask);
}
}