ShiftRights

Applicability

Product	Supported
Atlas 350 Accelerator Card	√
Atlas A3 training product/Atlas A3 inference product	x
Atlas A2 training product/Atlas A2 inference product	x
Atlas 200I/500 A2 inference product	x
Atlas inference product AI Core	x
Atlas inference product Vector Core	x
Atlas training product	x

Function Usage

Performs right shift on the source operand element-wise. The shift distance is determined by the scalarValue argument.

Performs logical right shift for the uint16_t/uint32_t data type while arithmetic right shift for the int16_t/int32_t data type.

A logical right shift discards the least significant bits and fills the most significant bits with 0.

An arithmetic right shift discards the least significant bits and replicates the sign bit into the most significant bits.

For example, the binary number 1010101010101010 (uint16_t) becomes 0101010101010101 after a logical right shift by 1 bit.

For example, the binary number 1010101010101010 (int16_t) becomes 1101010101010101 after an arithmetic right shift by 1 bit.

The binary number 1010101010101010 (int16_t) becomes 1111010101010101 after an arithmetic right shift by 3 bits.

Prototype

template <typename T = DefaultType, typename U, MaskMergeMode mode = MaskMergeMode::ZEROING, typename S>
__simd_callee__ inline void ShiftRights(S& dstReg, S& srcReg, U scalarValue, MaskReg& mask)

Parameters

**Table 1** Template parameters
Parameter	Description
T	Data type of the vector destination operand and source operand. For the Atlas 350 Accelerator Card, dstReg or srcReg supports the following data types: int8_t, uint8_t, int16_t, uint16_t, int32_t, uint32_t, int64_t, and uint64_t.
U	Data type of the scalar source operand. For the Atlas 350 Accelerator Card, dstReg or srcReg supports the data type of int16_t.
mode	Set it to MERGING or ZEROING. Currently, only ZEROING is supported. ZEROING: The elements that are not filtered by mask are set to zero in dst.
S	RegTensor type of dstReg, for example, RegTensor<uint16_t>. It is automatically inferred by the compiler and does not need to be specified.

**Table 2** Parameters
Parameter	Input/Output	Description
dstReg	Output	Destination operand. The type is RegTensor.
srcReg	Input	Source operand. The type is RegTensor.
scalarValue	Input	Source operand. The type is scalar. The value cannot be a negative number.
mask	Input	Valid indication of the source operand element operation. For details, see MaskReg.

Returns

None

Restrictions

None

Examples

template<typename T, typename U>
__simd_vf__ inline void ShiftRightsVF(__ubuf__ T* dstAddr, __ubuf__ T* srcAddr, U scalarValue, uint32_t count, uint32_t oneRepeatSize, uint16_t repeatTimes)
{
    AscendC::Reg::RegTensor<T> srcReg;
    AscendC::Reg::RegTensor<T> dstReg;
    AscendC::Reg::MaskReg mask;
    for (uint16_t i = 0; i < repeatTimes; i++) {
        AscendC::Reg::LoadAlign(srcReg, srcAddr + i * oneRepeatSize);
        mask = AscendC::Reg::UpdateMask<T>(count);
        AscendC::Reg::ShiftRights(dstReg, srcReg, scalarValue, mask);
        AscendC::Reg::StoreAlign(dstAddr + i * oneRepeatSize, dstReg, mask);
    }
}

Parent topic: Logical Computation