ShiftLefts

Applicability

Product	Supported
Atlas 350 Accelerator Card	√
Atlas A3 training product/Atlas A3 inference product	x
Atlas A2 training product/Atlas A2 inference product	x
Atlas 200I/500 A2 inference product	x
Atlas inference product AI Core	x
Atlas inference product Vector Core	x
Atlas training product	x

Function Usage

Performs logical left shift on the source operand element-wise. The shift distance is determined by the scalarValue argument.

The most significant bit is discarded and the least significant bit is padded with 0. For example, the 1-bit logical right shift of the binary number 1010101010101010 is 0101010101010100.

Prototype

template <typename T = DefaultType, typename U, MaskMergeMode mode = MaskMergeMode::ZEROING, typename S>
__simd_callee__ inline void ShiftLefts(S& dstReg, S& srcReg, U scalarValue, MaskReg& mask)

Parameters

**Table 1** Template parameters
Parameter	Description
T	Data type of the vector destination operand and source operand. For the Atlas 350 Accelerator Card, the supported data types are int8_t, uint8_t, int16_t, uint16_t, int32_t, uint32_t, int64_t, and uint64_t.
U	Data type of the scalar source operand. For the Atlas 350 Accelerator Card, the supported data type is int16_t.
mode	Set it to MERGING or ZEROING. Currently, only ZEROING is supported. ZEROING: The elements that are not filtered by mask are set to zero in dst.
S	RegTensor type of the destination operand, for example, RegTensor<half>. It is automatically inferred by the compiler and does not need to be specified.

**Table 2** Parameters
Parameter	Input/Output	Description
dstReg	Output	Destination operand. The type is RegTensor.
srcReg	Input	Source operand. The type is RegTensor. The source and destination operands must have the same data type.
scalarValue	Input	Number of bits for logical left shift. The type is scalar. The value cannot be a negative number.
mask	Input	Valid indication of the source operand element operation. For details, see MaskReg.

Returns

None

Restrictions

None

Examples

template<typename T, typename U>
__simd_vf__ inline void ShiftLeftsVF(__ubuf__ T* dstAddr, __ubuf__ T* src0Addr, U scalarValue, uint32_t count, uint32_t oneRepeatSize, uint16_t repeatTimes)
{
    AscendC::Reg::RegTensor<T> srcReg;
    AscendC::Reg::RegTensor<T> dstReg;
    AscendC::Reg::MaskReg mask;
    for (uint16_t i = 0; i < repeatTimes; i++) {
        AscendC::Reg::LoadAlign(srcReg, src0Addr + i * oneRepeatSize);
        mask = AscendC::Reg::UpdateMask<T>(count);
        AscendC::Reg::ShiftLefts(dstReg, srcReg, scalarValue, mask);
        AscendC::Reg::StoreAlign(dstAddr + i * oneRepeatSize, dstReg, mask);
    }
}

Parent topic: Logical Computation