Adds
Applicability
Product |
Supported |
|---|---|
Atlas 350 Accelerator Card |
√ |
x |
|
x |
|
x |
|
x |
|
x |
|
x |
Function Usage
Performs addition between a vector and a scalar element-wise using the following formula, where VL_T indicates the number of elements that can be processed by the Vector Unit in one iteration. For details about the value of RegTensor, see the description of VL_T.

Prototype
template <typename T = DefaultType, typename U, MaskMergeMode mode = MaskMergeMode::ZEROING, typename S> __simd_callee__ inline void Adds(S& dstReg, S& srcReg, U scalarValue, MaskReg& mask)
Parameters
Parameter |
Description |
|---|---|
T |
Data type of the vector destination operand and source operand. For the Atlas 350 Accelerator Card, the supported data types are int8_t, uint8_t, int16_t, uint16_t, half, bfloat16_t, int32_t, uint32_t, float, complex32, int64_t, uint64_t, and complex64. |
U |
Data type of the scalar source operand. For the Atlas 350 Accelerator Card, the supported data types are int8_t, uint8_t, int16_t, uint16_t, half, bfloat16_t, int32_t, uint32_t, float, complex32, int64_t, uint64_t, and complex64. |
mode |
Set it to MERGING or ZEROING.
|
S |
RegTensor type of dstReg, for example, RegTensor<half>. It is automatically inferred by the compiler and does not need to be specified. |
Parameter |
Input/Output |
Description |
|---|---|---|
dstReg |
Output |
Destination operand. The type is RegTensor. |
srcReg |
Input |
Source operand. The type is RegTensor. The source and destination operands must have the same data type. |
scalarValue |
Input |
Source operand. The type is scalar. The source and destination operands must have the same data type. |
mask |
Input |
Valid indication of the source operand element operation. For details, see MaskReg. |
Returns
None
Restrictions
None
Examples
template<typename T>
__simd_vf__ inline void AddsVF(__ubuf__ T* dstAddr, __ubuf__ T* srcAddr, T scalarValue, uint32_t count, uint32_t oneRepeatSize, uint16_t repeatTimes)
{
AscendC::Reg::RegTensor<T> srcReg;
AscendC::Reg::RegTensor<T> dstReg;
AscendC::Reg::MaskReg mask; ;
for (uint16_t i = 0; i < repeatTimes; i++) {
mask = AscendC::Reg::UpdateMask<T>(count);
AscendC::Reg::LoadAlign(srcReg, srcAddr + i * oneRepeatSize);
AscendC::Reg::Adds(dstReg, srcReg, scalarValue, mask);
AscendC::Reg::StoreAlign(dstAddr + i * oneRepeatSize, dstReg, mask);
}
}