ExpSub

Applicability

Product	Supported
Atlas 350 Accelerator Card	√
Atlas A3 training product/Atlas A3 inference product	x
Atlas A2 training product/Atlas A2 inference product	x
Atlas 200I/500 A2 inference product	x
Atlas inference product AI Core	x
Atlas inference product Vector Core	x
Atlas training product	x

Function Usage

Subtracts srcReg1 from srcReg0, uses the difference as the exponent of e for computation, and writes the result to dstReg based on mask.

When srcReg is of the float type, the formula is as follows: $\text{[math]}$

When srcReg is of the half type, the formula is as follows: $\text{[math]}$

Prototype

template <typename T = DefaultType, typename U = DefaultType, RegLayout layout = RegLayout::ZERO, MaskMergeMode mode = MaskMergeMode::ZEROING, typename S, typename V>
__simd_callee__ inline void ExpSub(S& dstReg, V& srcReg0, V& srcReg1, MaskReg& mask)

Parameters

**Table 1** Template parameters
Parameter	Description
T	Data type of the destination operand. For the Atlas 350 Accelerator Card, the supported data type is float.
U	Data type of the source operand. For the Atlas 350 Accelerator Card, the supported data types are half and float.
layout	RegLayout enum class: enum class RegLayout { UNKNOWN = -1, ZERO, ONE, TWO, THREE }; This API supports only RegLayout::ZERO and RegLayout::ONE. This parameter is used when the type of src is half. It does not take effect when the type is float. When the type is half, RegLayout::ZERO indicates that half elements are read from the even bits of b16 RegTensor and converted into float elements, and RegLayout::ONE indicates that half elements are read from the odd bits of b16 RegTensor and converted into float elements.
mode	Set it to MERGING or ZEROING. ZEROING: The elements that are not filtered by mask are set to zero in dst. MERGING: not supported currently.
S	RegTensor type of dstReg, for example, RegTensor<half>. It is automatically inferred by the compiler and does not need to be specified.
V	RegTensor type of srcReg0 or srcReg1, for example, RegTensor<half>. It is automatically inferred by the compiler and does not need to be specified.

**Table 2** Parameters
Parameter	Input/Output	Description
dstReg	Output	Destination operand. The type is RegTensor.
srcReg0	Input	Source operand. The type is RegTensor.
srcReg1	Input	Source operand. The type is RegTensor.
mask	Input	Valid indication of the source operand element operation. For details, see MaskReg.

Returns

None

Constraints

When the type of src is half, Vector Unit processes a maximum of VL/sizeof(float) half elements at a time, and only the even bits in mask are valid, as shown in the following figure:

Example

template<typename T, typename U>
static __simd_vf__ inline void ExpSubVF(__ubuf__ T* dstAddr, __ubuf__ U* src0Addr, __ubuf__ U* src1Addr, uint32_t count, uint32_t srcRepeatSize, uint32_t dstRepeatSize, uint16_t repeatTimes)
{
    AscendC::Reg::RegTensor<U> srcReg0;
    AscendC::Reg::RegTensor<U> srcReg1;
    AscendC::Reg::RegTensor<T> dstReg;
    AscendC::Reg::MaskReg mask;
    for (uint16_t i = 0; i < repeatTimes; i++) {
        mask = AscendC::Reg::UpdateMask<U>(count);
        AscendC::Reg::LoadAlign(srcReg0, src0Addr + i * srcRepeatSize);
        AscendC::Reg::LoadAlign(srcReg1, src1Addr + i * srcRepeatSize);
        AscendC::Reg::ExpSub<T, U, AscendC::Reg::RegLayout::ZERO, AscendC::Reg::MaskMergeMode::ZEROING>(dstReg, srcReg0, srcReg1, mask);
        AscendC::Reg::StoreAlign(dstAddr + i * dstRepeatSize, dstReg, mask);
    }
}

Parent topic: Compound Computation