AddC

Applicability

Product

Supported

Atlas 350 Accelerator Card

Atlas A3 training product/Atlas A3 inference product

x

Atlas A2 training product/Atlas A2 inference product

x

Atlas 200I/500 A2 inference product

x

Atlas inference product AI Core

x

Atlas inference product Vector Core

x

Atlas training product

x

Function Usage

Performs element-wise addition on input data srcReg0, srcReg1, and carry data carrySrc based on the mask, and writes the result to dstReg. If the sum of srcReg0, srcReg1 (converted to uint32_t), and the carry value carrySrc exceeds the maximum uint32_t value, write 1 to the corresponding 4-bit field in the MaskReg carry. Otherwise, write 0. The formula is as follows:

The following is an example of the carry operation:

  • For the int32_t type, the value range of a_i and b_i is [–2147483648,2147483647].
    • Assume that a_i = -2147483648, b_i = -2, and carrySrc_i = 1, the formula is as follows:

      (uint32_t)a_i + (uint32_t)b_i + (uint32_t)carrySrc_i = (uint64_t)uint_dst_i

      Because uint_dst_i >> 32 is greater than 0, carry[(i%64):4*(i%64)] = 1.

    • Assume that a_i = 2, b_i = 5, and carrySrc_i = 1, the formula is as follows:

      (uint32_t)a_i + (uint32_t)b_i + (uint32_t)carrySrc_i = (uint64_t)uint_dst_i

      Because uint_dst_i >> 32 equals to 0, carry[(i%64):4*(i%64)] = 0.

  • For the uint32_t type, the value range of a_i and b_i is [0, 4294967295].
    • Assume that a_i = 4294967295, b_i = 2, and carrySrc_i = 0, the formula is as follows:

      (uint32_t)a_i + (uint32_t)b_i + (uint32_t)carrySrc_i = (uint64_t)uint_dst_i

      Because uint_dst_i >> 32 is greater than 0, carry[(i%64):4*(i%64)] = 1.

    • Assume that a_i = 3, b_i = 2, and carrySrc_i = 0, the formula is as follows:

      (uint32_t)a_i + (uint32_t)b_i + (uint32_t)carrySrc_i = (uint64_t)uint_dst_i

      Because uint_dst_i >> 32 equals to 0, carry[(i%64):4*(i%64)] = 0.

Prototype

template <typename T = DefaultType, typename U>
__simd_callee__ inline void AddC(MaskReg& carry, U& dstReg, U& srcReg0, U& srcReg1, MaskReg& carrySrc, MaskReg& mask)

Parameters

Table 1 Parameters in the template

Parameter

Description

T

Operand data type.

For the Atlas 350 Accelerator Card, the supported data types are uint32_t and int32_t.

U

RegTensor type of operands, for example, RegTensor<uint32_t>. It is automatically inferred by the compiler and does not need to be specified.

Table 2 Parameters

Parameter

Input/Output

Description

carry

Output

Destination operand.

The type is MaskReg.

dstReg

Output

Destination operand.

The type is RegTensor.

srcReg0

Input

Source operand.

The type is RegTensor.

The three source operands must have the same data type as the destination operand.

srcReg1

Input

Source operand.

The type is RegTensor.

The three source operands must have the same data type as the destination operand.

carrySrc

Input

Source operand. Input carry value.

The type is MaskReg.

The three source operands must have the same data type as the destination operand.

For the Atlas 350 Accelerator Card, the supported data types are uint32_t and int32_t.

mask

Input

Valid indication of the source operand element operation. For details, see MaskReg.

Returns

None

Restrictions

None

Examples

template <typename T>
static __simd_vf__ inline void AddVF(__ubuf__ T* dst0Addr, __ubuf__ T* dst1Addr, __ubuf__ T* src0Addr, __ubuf__ T* src1Addr, uint32_t count, uint16_t repeatTimes, uint32_t oneRepeatSize){
    
    AscendC::Reg::RegTensor<T> srcReg0;
    AscendC::Reg::RegTensor<T> srcReg1;
    AscendC::Reg::RegTensor<T> dstReg0;
    AscendC::Reg::MaskReg mask;
    AscendC::Reg::MaskReg carry = AscendC::Reg::CreateMask<uint8_t>();
    for (uint16_t i = 0; i < repeatTimes; i++) {
        mask = AscendC::Reg::UpdateMask<T>(count);
        AscendC::Reg::LoadAlign(srcReg0, src0Addr + i * oneRepeatSize);
        AscendC::Reg::LoadAlign(srcReg1, src1Addr + i * oneRepeatSize);
        AscendC::Reg::Add(carry, dstReg0, srcReg0, srcReg1, mask);
        // 8*4B=32B align
        AscendC::Reg::StoreAlign<uint32_t, AscendC::Reg::MaskDist::DIST_NORM>((__ubuf__ uint32_t*)dst1Addr + i * 8, carry);
        AscendC::Reg::StoreAlign(dst0Addr + i * oneRepeatSize, dstReg0, mask);
    }
}