Mull
Applicability
|
Product |
Supported |
|---|---|
|
Atlas 350 Accelerator Card |
√ |
|
|
x |
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|
x |
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|
x |
|
|
x |
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|
x |
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|
x |
Function Usage
Multiplies the input data srcReg0 and srcReg1 element-wise based on the mask, writes the result to dstReg0, and writes the overflow part to dstReg1.

Prototype
template <typename T = DefaultType, typename U> __simd_callee__ inline void Mull(U& dstReg0, U& dstReg1, U& srcReg0, U& srcReg1, MaskReg& mask)
Parameters
|
Parameter |
Description |
|---|---|
|
T |
Operand data type. For the Atlas 350 Accelerator Card, the supported data types are uint32_t and int32_t. |
|
U |
RegTensor type of the source and destination operands, for example, RegTensor<uint32_t>. It is automatically inferred by the compiler and does not need to be specified. |
|
Parameter |
Input/Output |
Description |
|---|---|---|
|
dstReg0 |
Output |
Destination operand. The type is RegTensor. |
|
dstReg1 |
Output |
Destination operand. The type is RegTensor. |
|
srcReg0 |
Input |
Source operand. The type is RegTensor. Both of the source operands must have the same data type as the destination operand. |
|
srcReg1 |
Input |
Source operand. The type is RegTensor. Both of the source operands must have the same data type as the destination operand. |
|
mask |
Input |
Valid indication of the source operand element operation. For details, see MaskReg. |
Returns
None
Restrictions
None
Examples
template<typename T>
__simd_vf__ inline void MullVF(__ubuf__ T* dst0Addr, __ubuf__ T* dst1Addr, __ubuf__ T* src0Addr, __ubuf__ T* src1Addr, uint32_t count, uint32_t oneRepeatSize, uint16_t repeatTimes)
{
AscendC::Reg::RegTensor<T> srcReg0;
AscendC::Reg::RegTensor<T> srcReg1;
AscendC::Reg::RegTensor<T> dstReg0;
AscendC::Reg::RegTensor<T> dstReg1;
AscendC::Reg::MaskReg mask;
for (uint16_t i = 0; i < repeatTimes; i++) {
mask = AscendC::Reg::UpdateMask<T>(count);
AscendC::Reg::LoadAlign(srcReg0, src0Addr + i * oneRepeatSize);
AscendC::Reg::LoadAlign(srcReg1, src1Addr + i * oneRepeatSize);
AscendC::Reg::Mull(dstReg0, dstReg1, srcReg0, srcReg1, mask);
AscendC::Reg::StoreAlign(dst0Addr + i * oneRepeatSize, dstReg0, mask);
AscendC::Reg::StoreAlign(dst1Addr + i * oneRepeatSize, dstReg1, mask);
}
}