Div

Applicability

Product	Supported
Atlas 350 Accelerator Card	√
Atlas A3 training product/Atlas A3 inference product	x
Atlas A2 training product/Atlas A2 inference product	x
Atlas 200I/500 A2 inference product	x
Atlas inference product AI Core	x
Atlas inference product Vector Core	x
Atlas training product	x

Function Usage

Divides the input data srcReg0 and srcReg1 element-wise based on the mask and writes the result to dstReg. The formula is as follows:

$\text{[math]}$

Prototype

template <typename T = DefaultType, auto mode = MaskMergeMode::ZEROING, typename U>
__simd_callee__ inline void Div(U& dstReg, U& srcReg0, U& srcReg1, MaskReg& mask)

Parameters

**Table 1** Parameters in the template
Parameter	Description
T	Operand data type. For the Atlas 350 Accelerator Card, the supported data types are uint16_t, int16_t, half, uint32_t, int32_t, float, complex32, int64_t, uint64_t, and complex64.
mode	It can be set to the enumeration of MaskMergeMode or a pointer to a structure of DivSpecificMode. MaskMergeMode: Select the MERGING or ZEROING mode. ZEROING: The elements that are not filtered by mask are set to zero in dstReg. MERGING: This option is not supported currently. DivSpecificMode: enum class DivAlgo { INTRINSIC = 0, DIFF_COMPENSATION, PRECISION_1ULP_FTZ_TRUE, PRECISION_0ULP_FTZ_TRUE, PRECISION_0ULP_FTZ_FALSE, PRECISION_1ULP_FTZ_FALSE }; struct DivSpecificMode { MaskMergeMode mrgMode = MaskMergeMode::ZEROING, bool precisionMode = false; DivAlgo algo = DivAlgo::INTRINSIC; }; When precisionMode is true, higher precision division is enabled. The operation utilizes a difference compensation algorithm to derive the result, ensuring a maximum precision error of 0 ulp. Currently, this takes effect only for the float data type. algo: used to configure the subnormal mode. DivAlgo::INTRINSIC and DivAlgo::PRECISION_1ULP_FTZ_TRUE: The result is computed using a single instruction, with a maximum precision error of 1 ulp. DivAlgo::DIFF_COMPENSATION and DivAlgo::PRECISION_0ULP_FTZ_TRUE: The result is computed using the difference compensation algorithm, with a maximum precision error of 0 ulp. Currently, this algorithm supports only the float and complex64 data types. DivAlgo::PRECISION_0ULP_FTZ_FALSE: Subnormal data computation is supported. The result is computed using the difference compensation algorithm, with a maximum precision error of 0 ulp. Currently, this algorithm supports only the float data type. DivAlgo::PRECISION_1ULP_FTZ_FALSE: Subnormal data computation is supported. The result is computed using a single instruction, with a maximum precision error of 1 ulp. Currently, this algorithm supports only the half and float data types.
U	RegTensor type of the destination operand, for example, RegTensor<half>. It is automatically inferred by the compiler and does not need to be specified.

**Table 2** Parameters
Parameter	Input/Output	Description
dstReg	Output	Destination operand. The type is RegTensor.
srcReg0	Input	Source operand. The type is RegTensor. The source and destination operands must have the same data type.
srcReg1	Input	Source operand. The type is RegTensor. The source and destination operands must have the same data type.
mask	Input	Valid indication of the source operand element operation. For details, see MaskReg.

Returns

None

Restrictions

None

Examples

template<typename T>
__simd_vf__ inline void DivVF(__ubuf__ T* dstAddr, __ubuf__ T* src0Addr, __ubuf__ T* src1Addr, uint32_t count, uint32_t oneRepeatSize, uint16_t repeatTimes)
{
    AscendC::Reg::RegTensor<T> srcReg0;
    AscendC::Reg::RegTensor<T> srcReg1;
    AscendC::Reg::RegTensor<T> dstReg;
    AscendC::Reg::MaskReg mask;
    // High-precision mode
    // static constexpr AscendC::Reg::DivSpecificMode mode = {AscendC::Reg::MaskMergeMode::ZEROING, true};
    // Subnormal mode
    // static constexpr AscendC::Reg::DivSpecificMode mode = {AscendC::Reg::MaskMergeMode::ZEROING, true, DivAlgo::PRECISION_0ULP_FTZ_FALSE};
    for (uint16_t i = 0; i < repeatTimes; i++) {
        mask = AscendC::Reg::UpdateMask<T>(count);
        AscendC::Reg::LoadAlign(srcReg0, src0Addr + i * oneRepeatSize);
        AscendC::Reg::LoadAlign(srcReg1, src1Addr + i * oneRepeatSize);
        AscendC::Reg::Div(dstReg, srcReg0, srcReg1, mask);
        // High-precision or subnormal mode
        // AscendC::Reg::Div<T, &mode>(dstReg, srcReg0, srcReg1, mask);
        AscendC::Reg::StoreAlign(dstAddr + i * oneRepeatSize, dstReg, mask);
    }
}

Parent topic: Basic Arithmetic