Sub

Applicability

Product	Supported
Atlas 350 Accelerator Card	√
Atlas A3 training product/Atlas A3 inference product	x
Atlas A2 training product/Atlas A2 inference product	x
Atlas 200I/500 A2 inference product	x
Atlas inference product AI Core	x
Atlas inference product Vector Core	x
Atlas training product	x

Function Usage

Performs element-wise subtraction between the source operands srcReg0 and srcReg1 based on mask and writes the result to the destination operand dstReg. The formula is as follows:

$\text{[math]}$

If the borrowing result is generated when subtraction is performed between srcReg0 and srcReg1, the least significant bit of every four bits in the corresponding position of MaskReg carry is written as 0. Otherwise, it is written as 1.

Examples:

**Table 1** Examples
Data Type	Borrowing	Example
int32_t	No	a_i = 5, b_i = 2 dst_i = a_i - b_i = 3 Write 1 to the least significant bit of every four bits in the corresponding position in carry: carry_i = 1
int32_t	Yes	a_i = 5, b_i = -7 dst_i = a_i - b_i = 12 Write 0 to the least significant bit of every four bits in the corresponding position in carry: carry_i = 0
uint32_t	No	a_i = 5, b_i = 2, dst_i = a_i - b_i = 3 Write 1 to the least significant bit of every four bits in the corresponding position in carry: carry_i = 1
uint32_t	Yes	a_i = 5, b_i = 7 dst_i = a_i - b_i = -2 Write 0 to the least significant bit of every four bits in the corresponding position in carry: carry_i = 0

Prototype

The computation result does not retain the carry.

template <typename T = DefaultType, MaskMergeMode mode = MaskMergeMode::ZEROING, typename U>
__simd_callee__ inline void Sub(U& dstReg, U& srcReg0, U& srcReg1, MaskReg& mask)

The computation result retains the carry.

template <typename T = DefaultType, typename U>
__simd_callee__ inline void Sub(MaskReg& carry, U& dstReg, U& srcReg0, U& srcReg1, MaskReg& mask)

Parameters

**Table 2** Parameters in the template
Parameter	Description
T	Operand data type. For the Atlas 350 Accelerator Card, the supported data types are uint8_t, int8_t, uint16_t, int16_t, uint32_t, int32_t, half, float, bfloat16_t, uint64_t, int64_t, complex32, and complex64.
mode	Set it to MERGING or ZEROING. ZEROING: The elements that are not filtered by mask are set to zero in dstReg. MERGING: This option is not supported currently.
U	RegTensor type of the destination operand, for example, RegTensor<half>. It is automatically inferred by the compiler and does not need to be specified.

**Table 3** Parameters
Parameter	Input/Output	Description
dstReg	Output	Destination operand. The type is RegTensor.
srcReg0	Input	Source operand. The type is RegTensor. The source and destination operands must have the same data type.
srcReg1	Input	Source operand. The type is RegTensor. The source and destination operands must have the same data type.
carry	Output	Destination operand. Output carry value. The type is MaskReg.
mask	Input	Valid indication of the source operand element operation. For details, see MaskReg.

Returns

None

Restrictions

None

Examples

The computation result does not retain the carry.

template<typename T>
__simd_vf__ inline void SubVF(__ubuf__ T* dstAddr, __ubuf__ T* src0Addr, __ubuf__ T* src1Addr, uint32_t count, uint32_t oneRepeatSize, uint16_t repeatTimes)
{
    AscendC::Reg::RegTensor<T> srcReg0;
    AscendC::Reg::RegTensor<T> srcReg1;
    AscendC::Reg::RegTensor<T> dstReg;
    AscendC::Reg::MaskReg mask;    
    for (uint16_t i = 0; i < repeatTimes; i++) {
        mask = AscendC::Reg::UpdateMask<T>(count);
        AscendC::Reg::LoadAlign(srcReg0, src0Addr + i * oneRepeatSize);
        AscendC::Reg::LoadAlign(srcReg1, src1Addr + i * oneRepeatSize);
        AscendC::Reg::Sub(dstReg, srcReg0, srcReg1, mask);
        AscendC::Reg::StoreAlign(dstAddr + i * oneRepeatSize, dstReg, mask);
    }
}

The computation result retains the carry.

template <typename T>
__simd_vf__ inline void SubVF(__ubuf__ T* dst0Addr, __ubuf__ T* dst1Addr, __ubuf__ T* src0Addr, __ubuf__ T* src1Addr, uint32_t count, uint32_t repeatTimes, uint16_t oneRepeatSize){
    
    AscendC::Reg::RegTensor<T> srcReg0;
    AscendC::Reg::RegTensor<T> srcReg1;
    AscendC::Reg::RegTensor<T> dstReg0;
    AscendC::Reg::MaskReg mask;   
    AscendC::Reg::MaskReg carry = AscendC::Reg::CreateMask<uint8_t>();
    for (uint16_t i = 0; i < repeatTimes; i++) {
        mask = AscendC::Reg::UpdateMask<T>(count);
        AscendC::Reg::LoadAlign(srcReg0, src0Addr + i * oneRepeatSize);
        AscendC::Reg::LoadAlign(srcReg1, src1Addr + i * oneRepeatSize);
        AscendC::Reg::Sub(carry, dstReg0, srcReg0, srcReg1, mask);
        // 8*4B=32B align
        AscendC::Reg::StoreAlign<uint32_t, AscendC::Reg::MaskDist::DIST_NORM>((__ubuf__ uint32_t*)dst1Addr + i * 8, carry);
        AscendC::Reg::StoreAlign(dst0Addr + i * oneRepeatSize, dstReg0, mask);
    }
}

Parent topic: Basic Arithmetic