Moving Data into MaskReg

Applicability

Product	Supported
Atlas 350 Accelerator Card	√
Atlas A3 training product/Atlas A3 inference product	x
Atlas A2 training product/Atlas A2 inference product	x
Atlas 200I/500 A2 inference product	x
Atlas inference product AI Core	x
Atlas inference product Vector Core	x
Atlas training product	x

Function Usage

Indicates the Reg vector computation data movement interface, and is used to move data from UB or RegTensor to MaskReg.

Prototype

// Use AddrReg to store the offset when data is moved into MaskReg.
template <typename T, MaskDist dist = MaskDist::DIST_NORM>
__simd_callee__ inline void LoadAlign(MaskReg& mask, __ubuf__ T* srcAddr, AddrReg offset);
// Move data into MaskReg in the POST_MODE_NORMAL scenario.
template <typename T, MaskDist dist = MaskDist::DIST_NORM>
__simd_callee__ inline void LoadAlign(MaskReg& mask, __ubuf__ T* srcAddr);
// Move data into MaskReg in the POST_MODE_UPDATE scenario.
template <typename T, PostLiteral postMode, MaskDist dist = MaskDist::DIST_NORM>
__simd_callee__ inline void LoadAlign(MaskReg& mask, __ubuf__ T* &srcAddr, int32_t offset);
// Move data from RegTensor into MaskReg.
template <typename T = DefaultType, int16_t offset, typename U>
__simd_callee__ inline void MaskGenWithRegTensor(MaskReg& dst, U& srcReg);

Parameters

**Table 1** Parameters for using AddrReg to store the offset when data is moved into MaskReg
Parameter	Input/Output	Description
T	Input	Operand data type. The supported data types are b8, b16, and b32.
dist	Input	Movement mode. Use the MaskDist type. The values are as follows: DIST_NORM: The normal mode is used. The alignment constraint is VL/8 bytes. VL/8 bytes of data are moved. DIST_US: The alignment constraint is VL/16 bytes. In upsampling mode, VL/16 bytes of data are moved, and each bit is repeated once. DIST_DS: The alignment constraint is min(32, VL/4) bytes. In downsampling mode, VL/4 bytes of data are moved, and every other bit is discarded.
mask	Output	Destination operand, which is of the MaskReg type.
srcAddr	Input/Output	Start address of the source operand in the UB.
offset	Input	The actual UB start address for the movement is computed as: srcAddr + offset.

**Table 2** Parameters in the POST_MODE_NORMAL scenario for moving data into MaskReg
Parameter	Input/Output	Description
T	Input	Operand data type. The supported data types are b8, b16, b32, or b64.
dist	Input	Movement mode. Use the MaskDist type. The values are as follows: DIST_NORM: The normal mode is used. The alignment constraint is VL/8 bytes. VL/8 bytes of data are moved. DIST_US: The alignment constraint is VL/16 bytes. In upsampling mode, VL/16 bytes of data are moved, and each bit is repeated once. DIST_DS: The alignment constraint is min(32, VL/4) bytes. In downsampling mode, VL/4 bytes of data are moved, and every other bit is discarded.
mask	Output	Destination operand, which is of the MaskTensor type.
srcAddr	Input/Output	Start address of the source operand in the UB.

**Table 3** Parameters in the POST_MODE_UPDATE scenario for moving data into MaskReg
Parameter	Input/Output	Description
T	Input	Operand data type. The supported data types are b8, b16, b32, or b64.
dist	Input	Movement mode. Use the MaskDist type. The values are as follows: DIST_NORM: The normal mode is used. The alignment constraint is VL/8 bytes. VL/8 bytes of data are moved. DIST_US: The alignment constraint is VL/16 bytes. In upsampling mode, VL/16 bytes of data are moved, and each bit is repeated once. DIST_DS: The alignment constraint is min(32, VL/4) bytes. In downsampling mode, VL/4 bytes of data are moved, and every other bit is discarded.
postMode	Input	This parameter controls whether to enable post update. POST_MODE_NORMAL: In normal scenarios, the UB operand address is not updated. POST_MODE_UPDATE: This is used in the POST_MODE_UPDATE scenario. The UB address is used as both the input and output and is updated each time it is called.
mask	Output	Destination operand, which is of the MaskTensor type.
srcAddr	Input/Output	Start address of the source operand in the UB.
offset	Input	When the offset is of the int32_t type, the meanings of POST_MODE_NORMAL and POST_MODE_UPDATE are different. POST_MODE_NORMAL scenario: The actual UB start address for the movement is computed as: srcAddr + offset. POST_MODE_UPDATE scenario: The actual UB start address for the movement is srcAddr. After the movement, the address is updated as follows: srcAddr += offset.

**Table 4** Parameters for moving data from RegTensor into MaskReg
Parameter	Input/Output	Description
T	Input	Operand data type. The supported data types are b16 and b32.
U	Input	RegTensor type of the source operand, for example, RegTensor<half>. It is automatically inferred by the compiler and does not need to be specified.
dst	Output	Destination operand, which is of the MaskTensor type.
srcReg	Input	Source operand, which is of the RegTensor type.
offset	Input	offset that determines the start address for data movement in srcReg. When the data type is b16, the offset is computed as: offset x 16. Because VL is 256 bytes, the value of offset ranges from 0 to 15. Similarly, when the data type is b32, the offset is computed as: offset x 8, and the value of offset ranges from 0 to 31. When the data type is B16, it is computed by bit as follows: dst[i] = srcReg[(offset x VL/16) + (i/2)]. When the data type is B32, it is computed by bit as follows: dst[i] = srcReg[(offset*VL/32) + (i/4)].

Figure 1 Offset function diagram

Returns

None

Restrictions

None

Examples

template <typename T>
__simd_vf__ inline void LoadAlignVF(__ubuf__ T* dstAddr, __ubuf__ T* srcAddr, uint32_t count, uint32_t oneRepeatSize, uint16_t repeatTimes)
{
    AscendC::Reg::MaskReg mask;;
    for (uint16_t i = 0; i < repeatTimes; ++i) {
        mask = AscendC::Reg::UpdateMask<T>(count);
        AscendC::Reg::AddrReg offset = AscendC::Reg::CreateAddrReg<T>(i, oneRepeatSize);
        AscendC::Reg::LoadAlign(mask, srcAddr, offset);
        AscendC::Reg::StoreAlign(dstAddr, mask, offset);
    }
}

template <typename T, int16_t offset>
__simd_vf__ inline void MaskGenWithRegTensorVF(__ubuf__ T* dstAddr, __ubuf__ T* srcAddr)
{
    AscendC::Reg::RegTensor<T> srcReg;
    AscendC::Reg::MaskReg mask = AscendC::Reg::CreateMask<T>();
    AscendC::Reg::LoadAlign(srcReg, srcAddr);
    AscendC::Reg::MaskGenWithRegTensor<T, offset>(mask, srcReg);
    AscendC::Reg::StoreAlign(dstAddr, mask);
}

Parent topic: Reg Data Movement