DataSyncBarrier (ISASI)

Applicability

Product	Supported
Atlas 350 Accelerator Card	√
Atlas A3 training product/Atlas A3 inference product	x
Atlas A2 training product/Atlas A2 inference product	√
Atlas 200I/500 A2 inference product	√
Atlas inference product AI Core	x
Atlas inference product Vector Core	x
Atlas training product	x

Function Usage

Blocks the execution of subsequent instructions until all previous memory access instructions are executed (the memory location to be waited for can be controlled by parameters).

Prototype

template <MemDsbT arg0>
__aicore__ inline void DataSyncBarrier()

Parameters

**Table 1** Template parameters
Parameter	Description
arg0	Template parameter, indicating the memory location to be waited for. The type is MemDsbT. The options are as follows: ALL: Wait for all memory access instructions. DDR: Wait for the GM access instruction. UB: Wait for the UB access instruction. SEQ: Wait for the SEQ access instruction.

Returns

None

Constraints

None

Example

AscendC::Mmad(...);
AscendC::DataSyncBarrier<MemDsbT::ALL>(); // Wait for the completion of Mmad and all previous memory access instructions before executing FixPipe.
AscendC::Fixpipe(...);

Parent topic: Intra-Core Synchronization