LocalMemBar

Applicability

Product	Supported
Atlas 350 Accelerator Card	√
Atlas A3 training product / Atlas A3 inference product	x
Atlas A2 training product / Atlas A2 inference product	x
Atlas 200I/500 A2 inference product	x
Atlas inference product AI Core	x
Atlas inference product Vector Core	x
Atlas training product	x

Function Usage

Synchronizes different pipelines in the Reg vector computation macro function. This synchronization instruction specifies the source pipeline (src) and destination pipeline (dst). As shown in the following figure, the destination pipeline waits for all instructions on the source pipeline to complete before execution. In the read-write scenario, if the register used by the read instruction is the same as that used by the write instruction, register order-preserving can be triggered. In this case, instructions are executed in the code sequence, and no synchronization instruction needs to be inserted. If the register used by the read instruction is different from that used by the write instruction, a synchronization instruction needs to be inserted to ensure that the read and write instructions are executed in sequence. The same applies to the write-write scenario.

Figure 1 Pipeline waiting diagram

Prototype

template <MemType src, MemType dst> 
__simd_callee__ inline void LocalMemBar()

Parameters

**Table 1** Template parameters
Parameter	Description
src	Source pipeline. The type is MemType. For details, see Table 2.
dst	Destination pipeline. The type is MemType. For details, see Table 2.

**Table 2** MemType values
MemType Value	Meaning
VEC_STORE	Vector write to Unified Buffer pipeline in the SIMD_VF function. Instructions for moving data from the register to Unified Buffer include StoreAlign, StoreUnAlign, and Store.
VEC_LOAD	Vector read from Unified Buffer pipeline in the SIMD_VF function. Instructions for moving data from Unified Buffer to the register include LoadAlign, LoadUnAlign, and Load.
SCALAR_STORE	Scalar write to Unified Buffer pipeline in the SIMD_VF function. Instructions for writing scalar data to Unified Buffer include Duplicate.
SCALAR_LOAD	Scalar read from Unified Buffer pipeline in the SIMD_VF function. Instructions for reading scalar data from Unified Buffer include GetValue.
VEC_ALL	Vector read/write from/to Unified Buffer pipeline in the SIMD_VF function.
SCALAR_ALL	Scalar read/write from/to Unified Buffer pipeline in the SIMD_VF function.

**Table 3** src and dst combinations
src	dst
VEC_STORE	VEC_LOAD
VEC_LOAD	VEC_STORE
VEC_STORE	VEC_STORE
VEC_STORE	SCALAR_LOAD
VEC_STORE	SCALAR_STORE
VEC_LOAD	SCALAR_STORE
SCALAR_STORE	VEC_LOAD
SCALAR_STORE	VEC_STORE
SCALAR_LOAD	VEC_STORE
VEC_ALL	VEC_ALL
VEC_ALL	SCALAR_ALL
SCALAR_ALL	VEC_ALL

Returns

None

Constraints

None

Example

In the following example, dstPtr and src0Ptr point to the same Unified Buffer address. In the for loop, the same Unified Buffer address space is used for the vector read from Unified Buffer in the second loop and the vector write to Unified Buffer in the first loop. Therefore, the vector read from Unified Buffer in the second loop can be executed only after the vector write to Unified Buffer in the first loop is complete. You need to insert a synchronization point where VEC_LOAD waits for VEC_STORE to complete.

template<typename T>
__simd_vf__ inline void AddVF(__ubuf__ T* dstAddr, __ubuf__ T* src0Addr, __ubuf__ T* src1Addr, uint32_t count, uint32_t oneRepeatSize, uint16_t repeatTimes)
{
    AscendC::Reg::RegTensor<T> srcReg0;
    AscendC::Reg::RegTensor<T> srcReg1;
    AscendC::Reg::RegTensor<T> dstReg;
    AscendC::Reg::MaskReg mask;   
    for (uint16_t i = 0; i < repeatTimes; i++) {
        mask = AscendC::Reg::UpdateMask<T>(count);
        AscendC::Reg::LocalMemBar<AscendC::Reg::MemType::VEC_STORE, AscendC::Reg::MemType::VEC_LOAD>();
        AscendC::Reg::LoadAlign(srcReg0, src0Addr);
        AscendC::Reg::LoadAlign(srcReg1, src1Addr + i * oneRepeatSize);
        AscendC::Reg::Add(dstReg, srcReg0, srcReg1, mask);
        AscendC::Reg::StoreAlign(dstAddr, dstReg, mask);
    }
}

Parent topic: Synchronization Control