biu_group/aic_core_group/aiv_core_group (AI Core and AI Vector Bandwidth and Latency)

The AI Core and AI Vector bandwidth and latency data does not contain the summary information. The timeline information is displayed at the biu_group, aic_core_group, and aiv_core_group levels in the msprof_*.json file.

Applicable Products

Product	Supported
Ascend 950PR/Ascend 950DT	√
Atlas A3 training products/Atlas A3 inference products	√
Atlas A2 training products/Atlas A2 inference products	√
Atlas 200I/500 A2 inference products	x
Atlas inference products	x
Atlas training products	x

Data at biu_group, aic_core_group, and aiv_core_group Layers in msprof_*.json

The following uses the Atlas A3 training products/Atlas A3 inference products and Atlas A2 training products/Atlas A2 inference products data as an example.

Figure 1 biu_group

Figure 2 aic_core_group

Figure 3 aiv_core_group

**Table 1** Field description (biu_group)
Field	Description
Bandwidth Read	Bandwidth for the BIU bus interface to read instructions.
Bandwidth Write	Bandwidth for the BIU bus interface to write instructions.
Latency Read	Latency for the BIU bus interface to read instructions.
Latency Write	Latency for the BIU bus interface to write instructions.

The preceding biu_group level data applies to the Atlas A3 training products/Atlas A3 inference products and Atlas A2 training products/Atlas A2 inference products. For the Ascend 950PR/Ascend 950DT, the Biu Perf level (BIU instruction pipeline) is used instead. Its child layer is grouped by the dimension of Group{id}-{core ID}, for example, Group0-aiv0. The fields within each group are consistent with those at the biu_group level.

**Table 2** Field description (aic_core_group)
Field	Description
Cube	Cycle quantity and ratio of matrix operation instructions in the current sampling period.
Mte1	Cycle quantity and ratio of L1-to-L0A/L0B transfer instructions in the current sampling period.
Mte2	Cycle quantity and ratio of on-chip memory to AI Core movement instructions in the current sampling period.
Mte3	Cycle quantity and ratio of AI Core to on-chip memory movement instructions in the current sampling period.

**Table 3** Field description (aiv_core_group)
Field	Description
Mte1	Cycle quantity and ratio of L1-to-L0A/L0B transfer instructions in the current sampling period.
Mte2	Cycle quantity and ratio of on-chip memory to AI Core movement instructions in the current sampling period.
Mte3	Cycle quantity and ratio of AI Core to on-chip memory movement instructions in the current sampling period.
Scalar	Cycle quantity and ratio of scalar operation instructions in the current sampling period.
Vector	Cycle quantity and ratio of vector operation instructions in the current sampling period.

Parent topic: Profile Data File References