Basic Concepts

The Mobile Industry Processor Interface (MIPI) described in this document refers to the communications interface that uses the D-PHY transmission specifications at the physical layer and CSI-2 at the protocol layer.

The low-voltage differential signaling (LVDS) technology differentiates blanking regions and valid data by using the sync code. Sub-LVDS is a low-voltage variant of LVDS and is commonly used in Sony sensors.

The Scalable Low Voltage Signaling Embedded Clock (SLVS_EC) is an interface paralleled to the MIPI interface and used for capturing images with high frame rate and resolution.

A lane is a high-speed differential pair for connecting the TX end and RX end. It can be a clock lane or a data lane.

A link consists of a clock lane and at least one data lane between the TX end and RX end. In this document, link is a software concept, and each link contains two data lanes.

The MIPI interface uses the short packet in CSI-2 for synchronization, and the sub-LVDS uses the sync code to differentiate valid data and blanking regions. The sub-LVDS can be synchronized in either of the following modes:

• SOF and EOF indicate the start and end of a frame, respectively. SOL and EOL indicate the start and end of a line, respectively. The following figure shows the synchronization mode.
  Figure 1 SOF/EOF/SOL/EOL synchronization mode
  

Each sync code consists of four fields. The bit width of each field is consistent with that of pixel data. The first three fields are fixed benchmark codewords, and the fourth field is defined by the sensor vendor.

A sync code needs to be configured based on the specific sensor. The following figure shows the synchronization mode.

Figure 2 SAV/EAV synchronization mode

Digital overlap (DOL) indicates the WDR function of SONY.