aclrtDevAttr

Definition

      
       
         
         
           typedef enum { 
    ACL_DEV_ATTR_AICPU_CORE_NUM  = 1, 
    ACL_DEV_ATTR_AICORE_CORE_NUM = 101, 
    ACL_DEV_ATTR_CUBE_CORE_NUM = 102,
    ACL_DEV_ATTR_VECTOR_CORE_NUM = 201,      
    ACL_DEV_ATTR_WARP_SIZE = 202,
    ACL_DEV_ATTR_MAX_THREAD_PER_VECTOR_CORE,
    ACL_DEV_ATTR_UBUF_PER_VECTOR_CORE,
    ACL_DEV_ATTR_MAX_GRID_DIM_X = 205,
    ACL_DEV_ATTR_MAX_GRID_DIM_Y = 206,
    ACL_DEV_ATTR_MAX_GRID_DIM_Z = 207,
    ACL_DEV_ATTR_MAX_BLOCK_PER_GRID = 208,
    ACL_DEV_ATTR_MAX_THREADS_PER_BLOCK = 209,
    ACL_DEV_ATTR_MAX_BLOCK_DIM_X = 210,
    ACL_DEV_ATTR_MAX_BLOCK_DIM_Y = 211,
    ACL_DEV_ATTR_MAX_BLOCK_DIM_Z = 212,

    ACL_DEV_ATTR_TOTAL_GLOBAL_MEM_SIZE = 301,
    ACL_DEV_ATTR_L2_CACHE_SIZE = 302,

    ACL_DEV_ATTR_SMP_ID = 401U,
    ACL_DEV_ATTR_PHY_CHIP_ID = 402U,
    ACL_DEV_ATTR_SUPER_POD_DEVICE_ID = 403U,
    ACL_DEV_ATTR_SUPER_POD_SERVER_ID = 404U,
    ACL_DEV_ATTR_SUPER_POD_ID = 405U, 
    ACL_DEV_ATTR_CUST_OP_PRIVILEGE = 406U,
    ACL_DEV_ATTR_MAINBOARD_ID = 407U,
    ACL_DEV_ATTR_HD_CONNECT_TYPE = 408U,    

    ACL_DEV_ATTR_IS_VIRTUAL = 501U,

    ACL_DEV_ATTR_NPU_ARCH = 601U,
} aclrtDevAttr;

          

        

      
     

The enumerations are described as follows:

ACL_DEV_ATTR_AICPU_CORE_NUM
Number of AI CPUs.
ACL_DEV_ATTR_AICORE_CORE_NUM
Number of AI Cores.
ACL_DEV_ATTR_CUBE_CORE_NUM
Number of Cube Cores.
ACL_DEV_ATTR_VECTOR_CORE_NUM
Number of Vector Cores.
ACL_DEV_ATTR_WARP_SIZE
Number of threads in a warp. In the Single Instruction Multiple Thread (SIMT) programming model, a warp is a set of threads that execute the same instruction.

Only the Ascend 950PR / Ascend 950DT supports this option.

For product models that do not support this option, 0 is returned by default.
ACL_DEV_ATTR_MAX_THREAD_PER_VECTOR_CORE
Maximum number of threads that can reside on each Vector Core at the same time.

Only the Ascend 950PR / Ascend 950DT supports this option.

For product models that do not support this option, 0 is returned by default.
ACL_DEV_ATTR_UBUF_PER_VECTOR_CORE
Maximum size of the unified buffer that can be used on each Vector Core, in bytes.

Only the Ascend 950PR / Ascend 950DT supports this option.

For product models that do not support this option, 0 is returned by default.
ACL_DEV_ATTR_MAX_GRID_DIM_X
Maximum value of the grid dimension X, used for grid configuration of thread blocks in the SIMT programming model.

Only the Ascend 950PR / Ascend 950DT supports this option.

For product models that do not support this option, 0 is returned by default.

Note: A grid consists of multiple thread blocks and uses a three-dimensional structure. Dimensions X, Y, and Z indicate the thread block sizes in different dimensions. A thread block also uses a three-dimensional structure, with dimensions X, Y, and Z representing the number of threads in each dimension of the thread block.
ACL_DEV_ATTR_MAX_GRID_DIM_Y
Maximum value of the grid dimension Y, used for grid configuration of thread blocks in the SIMT programming model.

Only the Ascend 950PR / Ascend 950DT supports this option.

For product models that do not support this option, 0 is returned by default.
ACL_DEV_ATTR_MAX_GRID_DIM_Z
Maximum value of the grid dimension Z, used for grid configuration of thread blocks in the SIMT programming model.

Only the Ascend 950PR / Ascend 950DT supports this option.

For product models that do not support this option, 0 is returned by default.
ACL_DEV_ATTR_MAX_BLOCK_PER_GRID
Maximum number of blocks in each grid, used for grid configuration of thread blocks in the SIMT programming model.

Only the Ascend 950PR / Ascend 950DT supports this option.

For product models that do not support this option, 0 is returned by default.
ACL_DEV_ATTR_MAX_THREADS_PER_BLOCK
Maximum number of threads in each block, used for grid configuration of thread blocks in the SIMT programming model.

Only the Ascend 950PR / Ascend 950DT supports this option.

For product models that do not support this option, 0 is returned by default.
ACL_DEV_ATTR_MAX_BLOCK_DIM_X
Maximum value of the block dimension X, used for thread block configuration in the SIMT programming model.

Only the Ascend 950PR / Ascend 950DT supports this option.

For product models that do not support this option, 0 is returned by default.
ACL_DEV_ATTR_MAX_BLOCK_DIM_Y
Maximum value of the block dimension Y, used for thread block configuration in the SIMT programming model.

Only the Ascend 950PR / Ascend 950DT supports this option.

For product models that do not support this option, 0 is returned by default.
ACL_DEV_ATTR_MAX_BLOCK_DIM_Z
Maximum value of the block dimension Z, used for thread block configuration in the SIMT programming model.

Only the Ascend 950PR / Ascend 950DT supports this option.

For product models that do not support this option, 0 is returned by default.
ACL_DEV_ATTR_TOTAL_GLOBAL_MEM_SIZE
Total available memory on the device, in bytes.
ACL_DEV_ATTR_SMP_ID
Symmetric multiprocessing (SMP) ID, which is used to identify whether devices run on the same operating system.
ACL_DEV_ATTR_PHY_CHIP_ID
Physical chip ID.
ACL_DEV_ATTR_SUPER_POD_DEVICE_ID
SuperPoD device ID, which identifies a device in a SuperPoD product.
ACL_DEV_ATTR_SUPER_POD_SERVER_ID
SuperPoD server ID, which identifies a server in a SuperPoD product.
ACL_DEV_ATTR_SUPER_POD_ID
SuperPoD ID, which identifies a SuperPoD in the cluster.
ACL_DEV_ATTR_CUST_OP_PRIVILEGE
Whether the custom operator can execute more system call permissions.
The options are as follows:
- 0: The custom operator has limited system call permissions (for example, the write operation cannot be performed).
- 1: The custom operator can execute more system call permissions.
The Ascend 950PR / Ascend 950DT does not support this option.
ACL_DEV_ATTR_MAINBOARD_ID
Mainboard ID.
ACL_DEV_ATTR_HD_CONNECT_TYPE
Interconnection protocol between the host and device.

The options are as follows:
- 0: PCIe
- 1: Huawei Cache Coherence System (HCCS)
- 2: Unified Bus (UB)
Only the Ascend 950PR / Ascend 950DT supports this option.

For product models that do not support this option, an error is returned.
ACL_DEV_ATTR_IS_VIRTUAL
Whether the Ascend virtual instance is used.
- 0: A physical machine, instead of the Ascend virtual instance, is used.
- 1: The Ascend virtual instance is used, which may be a VM or container.
ACL_DEV_ATTR_NPU_ARCH
NPU architecture version.

The mapping between product models and NPU architecture versions is as follows:
- Ascend 950PR / Ascend 950DT : 3510
- Atlas A3 training products / Atlas A3 inference products : 2201
- Atlas A2 training products / Atlas A2 inference products : 2201
- Atlas 200I/500 A2 inference products : 3002
- Atlas inference products : 2002
- Atlas training products : 1001

Relationships Between AI Cores, Cube Cores, and Vector Cores

The definition of a Core helps you better understand the relationships between AI Cores, Cube Cores, and Vector Cores. A Core is a compute core with an independent Scalar compute unit. Generally, the Scalar compute unit provides multiple functions for the compute core, such as the single instruction multiple data (SIMD) instruction dispatch. Therefore, the Scalar compute unit is also called the intra-core scheduling unit. The AI data processing core unit varies with products. Currently, there are the following types:

The AI data processing core unit is an AI Core.
- In an AI Core, Cube and Vector share a Scalar scheduling unit.
  The following example uses Atlas training products .
- In an AI Core, a Cube and a Vector have their own Scalar scheduling units, which are also called a Cube Core and a Vector Core. In this case, a Cube Core and a group of Vector Cores are defined as an AI Core. The number of AI Cores is usually calculated based on the number of Cube Cores.
  The following example uses Atlas A2 training products / Atlas A2 inference products .
The AI data processing core unit consists of an AI Core and an independent Vector Core. The AI Core and Vector Core both have independent Scalar scheduling units.
The following example uses Atlas inference products .

Relationships Between SuperPoD IDs, SuperPoD Server IDs, and SuperPoD Device IDs

Parent topic: Data Types and Operation APIs