Non-contiguous Aligned Data Move-in

Applicability

Product	Supported
Atlas 350 Accelerator Card	√
Atlas A3 training product/Atlas A3 inference product	x
Atlas A2 training product/Atlas A2 inference product	x
Atlas 200I/500 A2 inference product	x
Atlas inference product AI Core	x
Atlas inference product Vector Core	x
Atlas training product	x

Function Usage

Indicates the Reg vector computation data movement interface, and is used to move non-contiguous aligned data from UB to RegTensor (in the unit of data block).

Prototype

// Normal scenario:
template <typename T = DefaultType, DataCopyMode dataMode, typename U>
__simd_callee__ inline void LoadAlign(U& dstReg, __ubuf__ T* srcAddr, uint32_t dataBlockStride, MaskReg& mask);
// POST_MODE_UPDATE scenario
template <typename T = DefaultType, DataCopyMode dataMode, PostLiteral postMode, typename U>
__simd_callee__ inline void LoadAlign(U& dstReg, __ubuf__ T*& srcAddr, uint32_t dataBlockStride, uint32_t repeatStride, MaskReg& mask);

Parameters

**Table 1** DataCopyMode template parameters
DataCopyMode Value	Description
DATA_BLOCK_COPY	It is used to select the movement mode in the non-contiguous alignment scenario. Currently, only the data block movement mode is supported, that is, data is moved by data block.

**Table 2** Parameters
Parameter	Input/Output	Description
T	Input	Template parameter. The supported data types are b8, b16, and b32.
postMode	Input	This parameter controls whether to enable post update. The value is of the PostLiteral type.
U	Input	RegTensor type, for example, RegTensor<half>. It is automatically inferred by the compiler and does not need to be specified.
dstReg	Output	Destination operand, which is of the RegTensor type.
srcAddr	Input/Output	Start address of the source operand in the UB.
dataBlockStride	Input	The interval between adjacent data blocks moved in a single operation (defined as the distance between the head of one data block and the head of the next). The unit is data block.
repeatStride	Input	The meaning of repeatStride is different under the POST_MODE_NORMAL and POST_MODE_UPDATE scenarios. POST_MODE_NORMAL scenario: The actual UB start address for the movement is computed as: srcAddr + (repeatStride × 32). POST_MODE_UPDATE scenario: The actual UB start address for the movement is srcAddr. After the movement, the address is updated as follows: srcAddr += repeatStride × 32.
mask	Input	MaskReg type, indicating which data blocks are valid during the movement. If any bit in the 32 bits corresponding to a data block is 1, the data block's data is moved to dst. If all the 32 bits corresponding to a data block are 0, the data block's data is not read, and the corresponding dst is set to 0. No error is reported even if the UB is out of bounds.

Returns

None

Restrictions

None

Examples

__simd_vf__ inline void Compute(__ubuf__ T* dstAddr, __ubuf__ T* srcAddr, uint16_t repeatTimes)
{
    AscendC::Reg::RegTensor<T> srcReg;
    AscendC::Reg::MaskReg mask = AscendC::Reg::CreateMask<T>();
    for (uint16_t i = 0; i < repeatTimes; ++i) {
        AscendC::Reg::LoadAlign<T, AscendC::Reg::DataCopyMode::DATA_BLOCK_COPY, AscendC::Reg::PostLiteral::POST_MODE_UPDATE>(srcReg, srcAddr, 1, i * 8, mask);
        AscendC::Reg::StoreAlign<T, AscendC::Reg::DataCopyMode::DATA_BLOCK_COPY, AscendC::Reg::PostLiteral::POST_MODE_UPDATE>(dstAddr, srcReg, 1, i * 8, mask);
    }
}

Parent topic: Reg Data Movement